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| S29NS-N MirrorBitTM Flash Family S29NS256N, S29NS128N, S29NS064N 256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory Data Sheet (Advance Information) S29NS-N MirrorBitTM Flash Family Cover Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S29NS-N_00 Revision A Amendment 13 Issue Date February 16, 2007 Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: "This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice." Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: "This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications." Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: "This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur." Questions regarding these document designations may be directed to your local sales office. 2 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family S29NS256N, S29NS128N, S29NS064N 256/128/64 Megabit (16/8/4M x 16-bit), CMOS 1.8 Volt-only Simultaneous Read/Write, Multiplexed, Burst Mode Flash Memory Data Sheet (Advance Information) Distinctive Characteristics Single 1.8V read, program and erase (1.70V to 1.95V) VersatileIOTM Feature - Device generates data output voltages and tolerates data input voltages as determined by the voltage on the VCCQ pin - 1.8V compatible I/O signals - Typical sector erase time of 150 ms for 16 Kword sectors and 800 ms sector erase time for 64 Kword sectors Security features Persistent Sector Protection - A command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector - Sectors can be locked and unlocked in-system at VCC level Multiplexed Data and Address for reduced I/O count - A15-A0 multiplexed as DQ15-DQ0 - Addresses are latched by AVD# control input when CE# low Simultaneous Read/Write operation - Data can be continuously read from one bank while executing erase/program functions in other bank - Zero latency between read and write operations Password Sector Protection - A sophisticated sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector using a user-defined 64-bit password Read access times at 66 MHz - Burst access times of 9/11 ns at industrial temperature range - Asynchronous random access times of 80 ns - Synchronous random access times of 80 ns Hardware Sector Protection - WP# protects the two highest sectors - All sectors locked when ACC = VIL Burst length - Continuous linear burst - 8/16/32 word linear burst with wrap around - 8/16/32 word linear burst without wrap around Handshaking feature - Provides host system with minimum possible latency by monitoring RDY Supports Common Flash Memory Interface (CFI) Software command set compatible with JEDEC 42.4 standards - Backwards compatible with Am29F and Am29LV families Secured Silicon Sector region - 256 words accessible through a command sequence - 128 words for the Factory Secured Silicon Sector - 128 words for the Customer Secured Silicon Sector Manufactured on 110 nm MirrorBitTM process technology Cycling endurance: 100,000 cycles per sector typical Data retention: 20 years typical Data# Polling and toggle bits - Provides a software method of detecting program and erase operation completion Power dissipation (typical values: 8 bits switching, CL = 30 pF) @ 66 MHz - - - - Continuous Burst Mode Read: 28 mA Simultaneous Operation: 50 mA Program/Erase: 19 mA Standby mode: 20 A Erase Suspend/Resume - Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Sector Architecture - Four 16 K word sectors (S29NS256N and S29NS128N) and four 8K word sectors (S29NS064N) in upper-most address range - Two-hundred-fifty-five 64-Kword sectors (S29NS256N), onehundred-twenty-seven 64-Kword sectors (S29NS128N) and one hundred twenty-seven 32Kword sectors (S29NS064N) - Sixteen banks (S29NS128N and S29NS256N) and eight banks (S29NS064N) Program Suspend/Resume - Suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation Unlock Bypass Program command - Reduces overall programming time when issuing multiple program command sequences High Performance - Typical word programming time of 40 s - Typical effective word programming time of 9.4 s utilizing a 32-Word Write Buffer at VCC Level - Typical effective word programming time of 6 s utilizing a 32-Word Write Buffer at ACC Level Packages - 48-ball Very Thin FBGA (S29NS256N) - 44-ball Very Thin FBGA (S29NS128N, S29NS064N) Publication Number S29NS-N_00 Revision A Amendment 13 Issue Date February 16, 2007 This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. Data Sheet (Advance Information) 1. General Description The S29NS256N, S29NS128N and S29NS064N are 256 Mb, 128 Mb and 64Mb (respectively), 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash memory devices, organized as 16,777,216, 8,388,608, and 4,194,304 words of 16 bits each. These devices use a single VCC of 1.70 to 1.95 V to read, program, and erase the memory array. A 9.0-volt ACC, may be used for faster program performance if desired. These devices can also be programmed in standard EPROM programmers. The devices are offered at the following speeds: Clock Speed 66 MHz Burst Access (ns) 11.0 Synch. Initial Access (ns) 80 Asynch. Initial Access (ns) 80 Output Loading 30 pF The devices operate within the temperature range of -25C to +85C, and are offered in Very Thin FBGA packages. 1.1 Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into sixteen banks. The device allows a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The devices are structured as shown in the following tables: S29NS256N Bank 0-14 Sectors Quantity 240 240 Mb total Size 64 Kwords 15 16 Mb total 64 Kwords Quantity 4 Bank 15 Sectors Size 16 Kwords S29NS128N Bank 0-14 Sectors Quantity 120 120 Mb total Size 64 Kwords 7 8 Mb total 64 Kwords Quantity 4 Bank 15 Sectors Size 16 Kwords S29NS064N Bank 0-6 Sectors Quantity 112 56 Mbits Size 32 Kwords 15 8 Mbits 32 Kwords Quantity 4 Bank 7 Sectors Size 8 Kwords The VersatileIOTM (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VCCQ pin. The devices use Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Output Enable (OE#) to control asynchronous read and write operations. For burst operations, the devices additionally require Ready (RDY) and Clock (CLK). This implementation allows easy interface with minimal glue logic to microprocessors/microcontrollers for high performance read operations. The devices offer complete compatibility with the JEDEC 42.4 single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device are similar to reading from other Flash or EPROM devices. 4 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) The host system can detect whether a program or erase operation is complete by using the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The devices are fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The devices also offer three types of data protection at the sector level. Persistent Sector Protection provides in-system, command-enabled protection of any combination of sectors using a single power supply at VCC. Password Sector Protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password. When at VIL, WP# locks the highest two sectors. Finally, when ACC is at VIL, all sectors are locked. The devices offer two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both modes. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster program times by requiring only two write cycles to program data instead of four. Additionally, Write Buffer Programming is available on this family of devices. This feature provides superior programming performance by grouping locations being programmed. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already fully programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The Program Suspend/Program Resume feature enables the user to put program on hold to read data from any sector that is not selected for programming. If a read is needed from the Persistent Protection area, Dynamic Protection area, or the CFI area, after an program suspend, then the user must use the proper command sequence to enter and exit this region. The program suspend/resume functionality is also available when programming in erase suspend (1 level depth only). The Erase Suspend/Erase Resume feature enables the user to put erase on hold to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Persistent Protection area, Dynamic Protection area, or the CFI area, after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The host system can detect whether a memory array program or erase operation is complete by using the device status bit DQ7 (Data# Polling), DQ6/DQ2 (toggle bits), DQ5 (exceeded timing limit), DQ3 (sector erase start timeout state indicator), and DQ1 (write to buffer abort). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The device also offers two types of data protection at the sector level. When at VIL, WP# locks the two outermost boot sectors at the top of memory. When the ACC pin = VIL, the entire flash memory array is protected. Spansion Inc. Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector. The data is programmed using hot electron injection. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 5 Data Sheet (Advance Information) Table Of Contents Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Simultaneous Read/Write Operations with Zero Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table Of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. 3. 4. 5. Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block Diagram of Simultaneous Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 S29NS256N - 48-Ball Very Thin FBGA Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 S29NS128N - 48-Ball Very Thin FBGA Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 S29NS064N - 44-Ball Very Thin FBGA Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 11 5.4 Special Package Handling Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Input/Output Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 VersatileIOTM (VIO) Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Requirements for Asynchronous Read Operation (Non-Burst) . . . . . . . . . . . . . . . . . . . . . . . 8.3 Requirements for Synchronous (Burst) Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Programmable Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Handshaking Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Simultaneous Read/Write Operations with Zero Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9 Accelerated Program and Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10 Write Buffer Programming Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.12 Advanced Sector Protection and Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.13 Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.14 Persistent Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.15 Persistent Sector Protection Mode Lock Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.16 Password Sector Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.17 64-bit Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.18 Password Mode Lock Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.19 Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Protection Mode . . . . . . 8.20 Hardware Data Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.21 WP# Boot Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.22 Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.23 Write Pulse "Glitch" Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.24 Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.25 Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.26 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.27 Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.28 RESET#: Hardware Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.29 Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.30 Secured Silicon Sector SectorFlash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 15 17 17 17 18 18 18 18 19 20 20 21 22 22 23 23 23 24 24 24 24 24 25 25 25 25 26 26 6. 7. 8. 9. 10. Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Set Configuration Register Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Read Configuration Register Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 37 37 6 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 11. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Enter/Exit Secured Silicon Sector Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Program Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.5 Accelerated Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.6 Write Buffer Programming Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.7 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.9 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.10 Program Suspend/Program Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.11 Lock Register Command Set Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.12 Password Protection Command Set Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.13 Non-Volatile Sector Protection Command Set Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.14 Global Volatile Sector Protection Freeze Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.15 Volatile Sector Protection Command Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 RDY: Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 DQ3: Sector Erase Start Timeout State Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.8 DQ1: Write to Buffer Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 39 40 40 41 41 43 44 45 46 47 47 48 49 51 51 55 55 57 57 57 59 59 59 60 12. 13. 14. 15. 16. 17. 18. 19. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 15.1 CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.1 VCC Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2 Synchronous/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3 Asynchronous Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.5 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 64 65 67 68 69 20. 21. 22. 23. Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 BGA Ball Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Physical Dimensions (S29NS256N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 22.1 VDC048--48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 11 x 10 mm Package. . . . . 77 Physical Dimensions (S29NS128N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 23.1 VDD044--44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8 mm Package . . . . . 78 23.2 VDE044--44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 7.7 x 6.2mm Package . . . . 79 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.1 Revision A (April 16, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.2 Revision A1 (June 28, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.3 Revision A2 (September 9, 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.4 Revision A3 (November 16, 2004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.5 Revision A3a (April 5, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.6 Revision A4 (April 12, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.7 Revision A5 (August 15, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.8 Revision A6 (August 24, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 80 80 80 81 81 82 82 82 24. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 7 Data Sheet (Advance Information) 24.9 24.10 24.11 24.12 24.13 24.14 24.15 Revision A7 (September 16, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision A8 (September 23, 2005) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision A9 (November 15, 2005). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision A10 (March 23, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision A11 (April 20, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision A12 (June 13, 2006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision A13 (February 16, 2007) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 83 83 83 83 83 84 8 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 2. Product Selector Guide Description Burst Frequency Max Initial Synchronous Access Time, ns (TIACC) Max Burst Access Time, ns (TBACC) Max Asynchronous Access Time, ns (TACC) Max CE# Access Time, ns (TCE) Max OE# Access Time, ns (TOE) 11.0 S29NS256N, S29NS128N, S29NS064N 66 MHz 80 11.0 80 3. Block Diagram VCCQ VCC VSS A/DQ15-A/DQ0 RDY Buffer RDY Erase Voltage Generator Input/Output Buffers WE# RESET# State Control Command Register ACC WP# PGM Voltage Generator Chip Enable Output Enable Logic Data Latch CE# OE# Y-Decoder Y-Gating Timer Address Latch VCC Detector X-Decoder Cell Matrix AVD# CLK Burst State Control Burst Address Counter Amax-A0 A/DQ15-A/DQ0 Amax-A16 Note Amax indicates the highest order address bit. Amax equals A23 for NS256N, and A22 for NS128N and A21 for S29NS064N. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 9 Data Sheet (Advance Information) 4. Block Diagram of Simultaneous Operation Circuit VCCQ VCC VSS Vssq Bank Address Latches and Control Logic Y-Decoder DQ15-DQ0 Bank 0 Amax-A0 X-Decoder OE# Bank Address Latches and Control Logic Y-Decoder DQ15-DQ0 Bank 1 ACC (Note 4) RESET# WE# CE# AVD# CLK WP# DQ15-DQ0 Amax-A0 Amax-A0 X-Decoder OE# Status DQ15- DQ0 RDY Control OE# STATE CONTROL & COMMAND REGISTER X-Decoder Latches and Control Logic Y-Decoder Bank Address Bank n-1 DQ15-DQ0 Amax-A0 Amax-A0 X-Decoder OE# Bank Address Latches and Control Logic Y-Decoder Bank n DQ15-DQ0 Notes 1. A15-A0 are multiplexed with DQ15-DQ0. 2. Amax indicates the highest order address bit. A23 (NS256N), A22 (NS128N), and A21 (NS064N). 3. n = 15 for NS256N and NS128N, n = 7 for NS064N. 10 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 5. 5.1 Connection Diagram S29NS256N - 48-Ball Very Thin FBGA Connection Diagram S29NS256N 48-Ball Very Thin FBGA Top View, Balls Facing Down NC NC NC NC A1 RDY B1 VCCQ C1 D1 A2 A21 B2 A16 C2 D2 A3 VSS B3 C3 D3 A4 CLK B4 C4 D4 A5 VCC B5 C5 D5 A6 B6 C6 D6 A7 B7 C7 D7 A8 A19 B8 A18 C8 D8 A9 A17 B9 C9 D9 A10 A22 B10 C10 D10 WE# ACC A20 AVD# A23 RESET# WP# CE# VSSQ VSS A/DQ7 A/DQ6A/DQ13A/DQ12A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# A/DQ15A/DQ14 VSSQ A/DQ5 A/DQ4A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 NC NC NC NC S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 11 Data Sheet (Advance Information) 5.2 S29NS128N - 48-Ball Very Thin FBGA Connection Diagram S29NS128N 44-Ball Very Thin FBGA Top View, Balls Facing Down NC NC A1 RDY B1 VCCQ C1 D1 A2 A21 B2 A16 C2 D2 A3 VSS B3 C3 D3 A4 CLK B4 C4 D4 A5 VCC B5 C5 D5 A6 B6 C6 D6 A7 B7 C7 D7 A8 A19 B8 A18 C8 D8 A9 A17 B9 C9 D9 A10 A22 B10 C10 D10 WE# ACC A20 AVD# NC RESET# WP# CE# VSSQ VSS A/DQ7 A/DQ6A/DQ13A/DQ12A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# A/DQ15A/DQ14 VSSQ A/DQ5 A/DQ4A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 NC NC 12 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 5.3 S29NS064N - 44-Ball Very Thin FBGA Connection Diagram S29NS064N 44-Ball Very Thin FBGA Top View, Balls Facing Down NC NC A1 RDY B1 VCCQ C1 D1 A2 A21 B2 A16 C2 D2 A3 VSS B3 C3 D3 A4 CLK B4 C4 D4 A5 VCC B5 C5 D5 A6 B6 C6 D6 A7 B7 C7 D7 A8 A19 B8 A18 C8 D8 A9 A17 B9 C9 D9 A10 NC B10 C10 D10 WE# ACC A20 AVD# NC RESET# WP# CE# VSSQ VSS A/DQ7 A/DQ6A/DQ13A/DQ12A/DQ3 A/DQ2 A/DQ9 A/DQ8 OE# A/DQ15A/DQ14 VSSQ A/DQ5 A/DQ4A/DQ11 A/DQ10 VCCQ A/DQ1 A/DQ0 NC NC 5.4 Special Package Handling Instructions Special handling is required for Flash Memory products in FBGA packages.The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 13 Data Sheet (Advance Information) 6. Input/Output Descriptions A23-A16 A22-A16 A21-A16 A/DQ15-A/DQ0 CE# OE# WE# VCC VCCQ VSS VSSQ NC RDY CLK = Address Inputs, S29NS256N = Address Inputs, S29NS128N = Address Inputs, S29NS064N = Multiplexed Address/Data input/output = Chip Enable Input. Asynchronous relative to CLK for the Burst mode = Output Enable Input. Asynchronous relative to CLK for the Burst mode = Write Enable Input = Device Power Supply (1.70V-1.95V) = Input/Output Power Supply (1.70V-1.95V) = Ground = Input/Output Ground = No Connect; not connected internally = Ready output; indicates the status of the Burst read. VOL= data invalid. VOH = data valid = The first rising edge of CLK in conjunction with AVD# low latches address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access = Address Valid input. Indicates to device that the valid address is present on the address inputs (address bits A15-A0 are multiplexed, address bits Amax-A16 are address only) VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs RESET# WP# = Hardware reset input. VIL= device resets and returns to reading array data = Hardware write protect input. VIL = disables writes to SA257-258 (S29NS256N), SA129-130 (S29NS128N) or SA129-130 (S29NS064N). Should be at VIH for all other conditions = At 9V, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables program and erase functions. Should be at VIH for all other conditions AVD# ACC 6.1 Logic Symbol 5 to 8 Amax - A16 CLK CE# OE# WE# RESET# AVD# WP# ACC RDY A/DQ15- A/DQ0 16 Amax indicates the highest order address bit. 14 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 7. Ordering Information The order number (Valid Combination) is formed by the following: S29NS 256 N 0P BJ W 00 0 PACKING TYPE 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel MODEL NUMBER (DYB PROTECT AFTER POWER-UP) 00 = DYB Protect after Power-up TEMPERATURE RANGE W = Wireless (-25C to +85C) PACKAGE TYPE BJ = Very Thin Fine-Pitch BGA Lead (Pb)-Free LF35 package SPEED OPTION (BURST FREQUENCY) 0P = 66 MHz PROCESS TECHNOLOGY N = 110 nm MirrorBitTM Technology FLASH DENSITY 256 = 256 Mb 128 = 128 Mb 064 = 64 Mb DEVICE FAMILY S29NS = 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash Memory with Multiplexed I/O Interface 7.1 Valid Combinations Consult the local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29NSxxxN Valid Combinations Base Ordering Part Number S29NS256N Package & Temperature BJW Model Number 00 Packing Type (Note 1, 2) 0, 2, 3 (Note 1) Package Marking NS256N0PBJW00 Speed Options (MHz) 66 Package Type 48-ball FBGA 10mm x 11mm VDC048 44-ball FBGA 9.2mm x 8.0mm VDD044 44-ball FBGA 7.7mm x 6.2mm VDE044 S29NS128N BJW 00 0, 2, 3 (Note 1) NS128N0PBJW00 66 S29NS064N BJW 00 0, 2, 3 (Note 1) NS064N0PBJW00 66 Notes 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 15 Data Sheet (Advance Information) 8. Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 8.1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 8.1 Device Bus Operations Operation Asynchronous Read Write Standby (CE#) Hardware Reset Burst Read Operations Load Starting Burst Address Advance Burst to next address with appropriate Data presented on the Data Bus Terminate current Burst read cycle Terminate current Burst read cycle via RESET# Terminate current Burst read cycle and start new Burst read cycle Legend L = Logic 0, H = Logic 1, X = Don't Care. Note Terminating the current Burst cycle is determined by the falling edge of AVD#, while starting a new Burst read cycle is determined by the rising edge of AVD#. L L H X L H L X X H H H H H H Addr In X X X X Addr In Burst Data Out HIGH Z HIGH Z I/O H H H L H X H X X CE# L L H X OE# L H X X WE# H L X X Amax-16 Addr In Addr In X X A/DQ15-0 I/O I/O HIGH Z HIGH Z RESET# H H H L CLK L H/L H/L X X X AVD# 8.1 VersatileIOTM (VIO) Control The VersatileIO (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VCCQ pin. 8.2 Requirements for Asynchronous Read Operation (Non-Burst) To read data from the memory array, the system must assert a valid address on Amax-A16 and A/DQ15-A/ DQ0 while AVD# and CE# are at VIL. WE# should remain at VIH. Note that CLK must remain at VIL during asynchronous read operations. The rising edge of AVD# latches the address, after which the system can drive OE# to VIL. The data will appear on A/DQ15-A/DQ0. (See Figure 19.4 on page 69.) Since the memory array is divided into banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the outputs. The output enable access time (tOE) is the delay from the falling edge of OE# to valid data at the output. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. 16 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 8.3 Requirements for Synchronous (Burst) Read Operation The device is capable of seven different burst read modes: continuous burst read; 8-, 16-, and 32-word linear burst reads with wrap around; and 8-, 16-, and 32-word linear burst reads without wrap around. 8.3.1 Continuous Burst When the device first powers up, it is enabled for asynchronous read operation. The device is automatically enabled for burst mode and addresses are latched on the first rising edge of CLK input, while AVD# is held low for one clock cycle. Prior to activating the clock signal, the system should determine how many wait states are desired for the initial word (tIACC) of each burst session. The system would then write the Set Configuration Register command sequence. The initial word is output tIACC after the rising edge of the first CLK cycle. Subsequent words are output tBACC after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has a fixed internal address boundary that occurs every 128 words, starting at address 00007Fh. The transition from the highest address 7FFFFFh to 000000h is also a boundary crossing. During a boundary crossing, there is a no additional latency between the valid read at address 00007F and the valid read at address 000080 (or between addresses offset from these values by the same multiple of 128 words) for frequencies equal to or lower than 66 Mhz. During the time the device is outputting data with the starting burst address not divisible by four, additional waits are required. The RDY output indicates this condition to the system by deasserting. Table 8.2 through Table 8.5 shows the address latency as a function of variable wait states. Table 8.2 Address Latency for 7, 6, and 5 Wait States Word 0 1 7, 6, and 5 ws 2 3 D2 D3 D3 1 ws 1 ws 1 ws 1 ws 1 ws D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D0 D1 D1 D2 D2 D3 D3 1 ws D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 Table 8.3 Address Latency for 4 Wait States Word 0 1 4 ws 2 3 D2 D3 D3 1 ws 1 ws 1 ws D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 D9 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 Table 8.4 Address Latency for 3 Wait States Word 0 1 2 3 3 ws D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 D4 D4 D3 D4 D5 D5 D4 D5 D6 D6 D5 D6 D7 D7 D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 17 Data Sheet (Advance Information) Table 8.5 Address Latency for 2 Wait States Word 0 1 2 ws 2 3 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 D9 D10 D10 D11 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 Table 8.6 through Table 8.8 show the address/boundary crossing latency for variable wait state if a boundary crossing occurs during initial access Table 8.6 Address/Boundary Crossing Latency for 7, 6, and 5 Wait States Word 0 1 7, 6, and 5 ws 2 3 D2 D3 D3 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws 1 ws D4 D4 D5 D5 D6 D6 D7 D7 D0 D1 D1 D2 D2 D3 D3 1 ws 1 ws 1 ws D4 D4 D5 D5 D6 D6 D7 D7 Table 8.7 Address/Boundary Crossing Latency for 4 Wait States Word 0 1 4 ws 2 3 D2 D3 D3 1 ws 1 ws 1 ws 1 ws 1 ws D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D0 D1 D1 D2 D2 D3 D3 1 ws D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 Figure 8.1 Address/Boundary Crossing Latency for 3 Wait States Word 0 1 3 ws 2 3 D2 D3 D3 1 ws 1 ws 1 ws D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 D9 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8 D9 Table 8.8 Address/Boundary Crossing Latency for 2 Wait States Word 0 1 2 3 2 ws D0 D1 D2 D3 D1 D2 D3 1 ws D2 D3 D4 D4 D3 D4 D5 D5 D4 D5 D6 D6 D5 D6 D7 D7 D6 D7 D8 D8 D7 D8 D9 D9 D8 D9 D10 D10 The device will continue to output continuous, sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location, until the system asserts CE# high, RESET# low, or AVD# low in conjunction with a new address. See Table 8.1 on page 16. The reset command does not terminate the burst read operation. If the host system crosses a 128 word line boundary while reading in burst mode, and the device is not programming or erasing, no additional latency will occur as described above. If the host system crosses the bank boundary while the device is programming or erasing, the device will provide asynchronous read status information. The clock will be ignored. After the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and AVD# pulse. 18 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 8.3.2 8-, 16-, and 32-Word Linear Burst with Wrap Around These three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. In each of these modes, the burst addresses read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode (see Table 8.9.) Table 8.9 Burst Address Groups Mode 8-word 16-word 32-word Group Size 8 words 16 words 32 words Group Address Ranges 0-7h, 8-Fh, 10-17h, 18-1Fh... 0-Fh, 10-1Fh, 20-2Fh, 30-3Fh... 00-1Fh, 20-3Fh, 40-5Fh, 60-7Fh... As an example: if the starting address in the 8-word mode is 3Ah, and the burst sequence would be 3A-3B3C-3D-3E-3F-38-39h. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence on the starting address written to the device, and then wraps back to the first address in the selected address group and terminates the burst read. Note that in these three burst read modes the address pointer does not cross the boundary that occurs every 128 words; thus, no wait states are inserted (except during the initial access). 8.3.3 8-, 16-, and 32-Word Linear Burst without Wrap Around In these modes, a fixed number of words (predefined as 8, 16, or 32 words) are read from consecutive addresses starting with the initial word, which is written to the device. When the address is at the end of the group address range (see Burst Address Groups Table), the burst read operation stops and the RDY output goes low. There is no group limitation and is different from the Linear Burst with Wrap Around. As an example, for 8-word length Burst Read, if the starting address written to the device is 3A, the burst sequence would be 3A-3B-3C-3D-3E-3F-40-41h, and the read operation will be terminated after all eight words. The 16-word and 32-word modes would operate in a similar fashion and continuously read to the predefined 16 or 32 words accordingly. Note: In this burst read mode, the address pointer may cross the boundary that occurs every 128 words. 8.4 Programmable Wait State The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD# is driven active before data will be available. Upon power up, the device defaults to the maximum of seven total cycles. The total number of wait states is programmable from two to seven cycles. For further details, see Set Configuration Register Command Sequence on page 39. 8.5 Configuration Register The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, burst length, RDY configuration, and synchronous mode active. 8.6 Handshaking Feature The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. The host system should use the configuration register to set the number of wait states for optimal burst mode operation. The initial word of burst data is indicated by the rising edge of RDY after OE# goes low. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 19 Data Sheet (Advance Information) 8.7 Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in one of the other banks of memory. An erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). Figure 19.13 on page 77 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the table DC Characteristics on page 64 for read-while-program and read-while-erase current specifications. 8.8 Writing Commands/Command Sequences The device has inputs/outputs that accept both address and data information. To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive AVD# and CE# to VIL, and OE# to VIH when providing an address to the device, and drive WE# and CE# to VIL, and OE# to VIH. when writing commands or data. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. An erase operation can erase one sector, multiple sectors, or the entire device. Table 14-17 indicates the address space that each sector occupies. The device address space is divided into multiple banks. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "sector address" is the address bits required to uniquely select a sector. Refer to the DC Characteristics table for write mode current specifications. The section AC Characteristics on page 66 contains timing specification tables and timing diagrams for write operations. 8.9 Accelerated Program and Erase Operations The device offers accelerated program and erase operation through the ACC function. ACC is primarily intended to allow faster manufacturing throughput at the factory and not to be used in system operations. If the system asserts VHH on this input, the device automatically enters the aforementioned Unlock Bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. The system can then use the abbreviated Embedded Programming command and Write Buffer Load command sequence provided by the Unlock Bypass mode. Note that if a "Write-to-Buffer-Abort Reset" is required while in Unlock Bypass mode, the full 3-cycle RESET command sequence must be used to reset the device. Removing VHH from the ACC input, upon completion of the embedded program or erase operation, returns the device to normal operation. Note that sectors must be unlocked prior to raising ACC to VHH. Note that the ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. In addition, the ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. When at VIL, ACC locks all sectors. ACC should be at VIH for all other conditions. 8.10 Write Buffer Programming Operation Write Buffer Programming allows the system to write a maximum of 32 words in one programming operation. This results in a faster effective word programming time than the standard "word" programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. At this point, the system writes the number of "word locations minus 1" that will be loaded into the page buffer at the Sector Address in which programming will occur. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the "Program Buffer to Flash" confirm command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. (NOTE: The number loaded = the number of locations to program minus 1. For example, if the system will program 6 address locations, then 05h should be written to the device.) The system then writes the starting address/data combination. This starting address is the first address/data pair to be programmed, and selects the "write-buffer-page" address. All subsequent address/data pairs must fall within the "selected-write-buffer-page", and be loaded in sequential order. The "write-buffer-page" is selected by using the addresses AMAX-A5 where AMAX is A23 for S29NS256N, A22 for S29NS128N and A21 for S29NS064N. 20 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) The "write-buffer-page" addresses must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple "write-buffer-pages". This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected "write-buffer-page", the operation will ABORT.) After writing the Starting Address/Data pair, the system then writes the remaining address/data pairs into the write buffer. Write buffer locations must be loaded in sequential order. Note that if a Write Buffer address location is loaded multiple times, the "address/data pair" counter will be decremented for every data load operation. Also, the last data loaded at a location before the "Program Buffer to Flash" confirm command will be programmed into the device. It is the software's responsibility to comprehend ramifications of loading a write-buffer location more than once. The counter decrements for each data load operation, NOT for each unique write-buffer-address location. Once the specified number of write buffer locations have been loaded, the system must then write the "Program Buffer to Flash" command at the Sector Address. Any other address/data write combinations will abort the Write Buffer Programming operation. The device will then "go busy". The Data Bar polling techniques should be used while monitoring the last address location loaded into the write buffer. This eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm command at the last loaded address location, and then data bar poll at that same address. DQ7, DQ6, DQ5, DQ2, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer "embedded" programming operation can be suspended using the standard suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device will return to READ mode. The Write Buffer Programming Sequence can be ABORTED under any of the following conditions: Load a value that is greater than the page buffer size during the "Number of Locations to Program" step. Write to an address in a sector different than the one specified during the "Write-Buffer-Load" command. Write an Address/Data pair to a different write-buffer-page than the one selected by the "Starting Address" during the "write buffer data loading" stage of the operation. Write data other than the "Confirm Command" after the specified number of "data load" cycles. The ABORT condition is indicated by DQ1 = 1, DQ7 = DATA# (for the "last address location loaded"), DQ6 = TOGGLE, DQ5 = 0. This indicates that the Write Buffer Programming Operation was ABORTED. A "Write-toBuffer-Abort reset" command sequence is required when using the Write-Buffer-Programming features in Unlock Bypass mode. Note: The Secured Silicon sector, autoselect, and CFI functions are unavailable when a program operation is in progress. Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. Write buffer programming is allowed in any sequence of memory (or address) locations. These flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. However, programming the same word address multiple times without intervening erases requires a modified programming method. Please contact your local SpansionTM representative for details. 8.11 Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (which is separate from the memory array) on DQ15- DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. The autoselect codes can also be accessed insystem. When verifying sector protection, the sector address must appear on the appropriate highest order address bits. The remaining address bits are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The autoselect codes can also be accessed in-system through the command register. The command sequence is illustrated in Table 11.4, Command Definitions on page 54. Note that if a Bank Address (BA) on address bits A23, A22, A21, and A20 for the NS256N, A22, A21, A20, A19 for the NS128N and A21, A20, and A19 for the NS064N, is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 21 Data Sheet (Advance Information) To access the autoselect codes, the host system must issue the autoselect command via the command register, as shown in Table 11.4, Command Definitions on page 54. 8.12 Advanced Sector Protection and Unprotection This advanced security feature provides an additional level of protection to all sectors against inadvertent program or erase operations. The advanced sector protection feature disables both programming and erase operations in any sector while the advanced sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection can be implemented using either of the two methods Hardware method Software method Persistent/Password Sector Protection is achieved by using the software method while the sector protection with WP# pin is achieved by using the hardware method. All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable nonvolatile bits that define which sector protection method will be used. Persistent Mode Lock Bit Password Mode Lock Bit If the customer decides to continue using the Persistent Sector Protection method, they must set the Persistent Mode Lock Bit. This will permanently set the part to operate only using Persistent Sector Protection. However, if the customer decides to use the Password Sector Protection method, they must set the Password Mode Lock Bit. This will permanently set the part to operate only using Password Sector Protection. It is important to remember that setting either the Persistent Mode Lock Bit or the Password Mode Lock Bit permanently selects the protection mode. It is not possible to switch between the two methods once a locking bit has been set. It is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. If both are selected to be set at the same time, the operation will abort. This is done so that it is not possible for a system program or virus to later set the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Sector Protection Mode. The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at the factory prior to shipping the device through Spansion programming services. Contact an Spansion representative for details. 8.13 Sector Protection The device features several levels of sector protection, which can disable both the program and erase operations in certain sectors. Persistent Sector Protection A software enabled command sector protection method that replaces the old 12 V controlled protection method. Password Sector Protection A highly sophisticated software enabled protection method that requires a password before changes to certain sectors or sector groups are permitted WP# Hardware Protection A write protect pin (WP#) can prevent program or erase operations in the outermost sectors.The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen. 22 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 8.14 Persistent Sector Protection The Persistent Sector Protection method replaces the old 12 V controlled protection method while at the same time enhancing flexibility by providing three different sector protection states: Persistently Locked--A sector is protected and cannot be changed. Dynamically Locked--The sector is protected and can be changed by a simple command Unlocked--The sector is unprotected and can be changed by a simple command In order to achieve these states, three types of "bits" namely Persistent Protection Bit (PPB), Dynamic Protection Bit (DYB), and Persistent Protection Bit Lock (PPB Lock) are used to achieve the desired sector protection scheme: 8.14.1 Persistent Protection Bit (PPB) PPB is used to as an advanced security feature to protect individual sectors from being programmed or erased thereby providing additional level of protection. Every sector is assigned a Persistent Protection Bit. Each PPB is individually programmed through the PPB Program Command. However all PPBs are erased in parallel through the All PPB Erase Command. Prior to erasing, these bits don't have to be pre programmed. The Embedded Erase algorithm automatically preprograms and verifies prior to an electrical erase. The system is not required to provide any controls or timings during these operations. The PPBs retain their state across power cycles because they are Non-Volatile. The PPBs has the same endurance as the flash memory. 8.14.2 Persistent Protection Bit Lock (PPB Lock Bit) in Persistent Sector Protection Mode PPB Lock Bit is a global volatile bit and provides an additional level of protection to the sectors. When programmed (set to "0"), all the PPBs are locked and hence none of them can be changed. When erased (cleared to "1"), the PPBs are changeable. There is only one PPB Lock Bit in every device. Only a hardware reset or a power-up clears the PPB Lock Bit. It is to be noted that there is no software solution, i.e. command sequence to unlock the PPB Lock Bit. Once all PPBs are configured to the desired settings, the PPB Lock Bit may be set (programmed to "0"). The PPB Lock Bit is set by issuing the PPB Lock Bit Set Command. Programming or setting the PPB Lock Bit disables program and erase commands to all the PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock Bit is to go through a hardware or power-up reset. System boot code can determine if any changes to the PPB are needed e.g. to allow new system code to be downloaded. If no changes are needed then the boot code can disable the PPB Lock Bit to prevent any further changes to the PPBs during system operation. 8.14.3 Dynamic Protection Bit (DYB) DYB is a security feature used to protect individual sectors from being programmed or erased inadvertently. It is a volatile protection bit and is assigned to each sector. Upon power-up, the contents of all DYBs are set (programmed to "0"). Each DYB can be individually modified through the DYB Set Command or the DYB Clear Command. The Protection Status for a particular sector is determined by the status of the PPB and the DYB relative to that sector. For the sectors that have the PPBs cleared (erased to "1"), the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Set or Clear command sequences, the DYBs will be set (programmed to "0") or cleared (erased to "1"), thus placing each sector in the protected or unprotected state respectively. These states are the so-called Dynamic Locked or Unlocked states due to the fact that they can switch back and forth between the protected and unprotected states. This feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set (programmed to "0") or cleared (erased to "1") as often as needed. When the parts are first shipped, the PPBs are cleared (erased to "1") and upon power up or reset, the DYBs are set (programmed to "0"). The PPB Lock Bit defaults to the cleared state (erased to "1") after power up and the PPBs retain their previous state as they are non-volatile. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 23 Data Sheet (Advance Information) Note: Dynamic protection bits revert back to their default values after programming device's "Lock Register." It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Set command sequence is all that is necessary. The DYB Set or Clear command for the dynamic sectors signify protected or unprotected state of the sectors respectively. However, if there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB Lock Bit once again will lock the PPBs, and the device operates normally again. Note: To achieve the best protection, it's recommended to execute the PPB Lock Bit Set command early in the boot code, and protect the boot code by holding WP# = VIL. Note that the PPB and DYB bits have the same function when ACC = VHH as they do when ACC = VIH. Table 8.10 Sector Protection Schemes DYB 1 0 1 0 1 0 1 0 PPB 1 1 0 0 1 1 0 0 PPB Lock 1 1 1 1 0 0 0 0 Sector Unprotected Sector Protected through DYB Sector Protected through PPB Sector Protected through PPB and DYB Sector Unprotected Sector Protected through DYB Sector Protected through PPB Sector Protected through PPB and DYB Sector State Table 8.10 contains all possible combinations of the DYB, PPB, and PPB Lock relating to the status of the sector. In summary, if the PPB is set (programmed to "0"), and the PPB Lock is set (programmed to "0"), the sector is protected and the protection can not be removed until the next power cycle clears (erase to "1") the PPB Lock Bit. Once the PPB Lock Bit is cleared (erased to "1"), the sector can be persistently locked or unlocked. Likewise, if both PPB Lock Bit or PPB is cleared (erased to "1") the sector can then be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program or erase command to a protected sector enables status polling and returns to read mode without having modified the contents of the protected sector. The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. 8.15 Persistent Sector Protection Mode Lock Bit A Persistent Mode Lock Bit exists to guarantee that the device remain in software sector protection. Once programmed (set to "0"), the Persistent Mode Lock Bit prevents programming of the Password Mode Lock Bit. This guarantees that now, a hacker cannot place the device in Password Sector Protection Mode. 8.16 Password Sector Protection The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection Mode and the Password Sector Protection Mode: When the device is first powered up, or comes out of a reset cycle, the PPB Lock Bit is set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock Bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. 24 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) The password is stored in a one-time programmable (OTP) region of the flash memory. Once the Password Mode Lock Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock Bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock Bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 1 s delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. 8.17 64-bit Password The 64-bit Password is located in a non-erasable region of the FLash and is accessible through the use of the Password Program and Verify commands (see Password Protection Command Set Definitions on page 50). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device. 8.18 Password Mode Lock Bit In order to select the Password Sector Protection scheme, the customer must first program the password. Spansion Inc. recommends that the password be somehow correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations. Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: It permanently sets the device to operate using the Password Sector Protection Mode. It is not possible to reverse this function. It also disables all further commands to the password region. All program and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Sector Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Lock Bit, there will be no way to clear the PPB Lock Bit. The Password Mode Lock Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Lock Bit is not erasable. Once Password Mode Lock Bit is programmed, the Persistent Mode Lock Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 8.19 Persistent Protection Bit Lock (PPB Lock Bit) in Password Sector Protection Mode The Persistent Protection Bit Lock (PPB Lock Bit) is a volatile bit that reflects the state of the Password Mode Lock Bit after power-up reset. If the Password Mode Lock Bit is also set, after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command to enter the entire password clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock Bit Set command sets the PPB Lock Bit to a "1". If the Password Mode Lock Bit is not set (device is operating in the default Persistent Protection Mode). The Password Unlock command is ignored in Persistent Sector Protection Mode. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 25 Data Sheet (Advance Information) 8.20 Hardware Data Protection Mode The device offers two types of data protection at the sector level: 1. When WP# is at VIL, the two outermost sectors at the top are locked (device specific). 1. When ACC is at VIL, all sectors are locked. SA257 and SA258 are locked (S29NS256N) SA129 and SA130 are locked (S29NS128N) SA129 and SA130 are locked (S29NS064N) The write protect pin (WP#) adds a final level of hardware program and erase protection to the boot sectors. The boot sectors are the two sectors containing the highest set of addresses in these top-boot-configured devices. For the none boot option, the WP# hardware feature is not available. When this pin is low it is not possible to change the contents of these top sectors. These sectors generally hold system boot code. So, the WP# pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. The following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. 8.20.1 Write Protect (WP#) The Write Protect feature provides a hardware method of protecting the two outermost sectors. This function is provided by the WP# pin and overrides the previously discussed Sector Protection/Unprotection method. If the system asserts VIL on the WP# pin, the device disables program and erase functions in the "top" boot sectors. If the system asserts VIH on the WP# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. 8.21 WP# Boot Sector Protection The WP# signal will be latched at a specific time in the embedded program or erase sequence. To prevent a write to the top two sectors, WP# must be asserted (WP#=VIL) on the last write cycle of the embedded sequence (i.e., 4th write cycle in embedded program, 6th write cycle in embedded erase). If selecting multiple sectors for erasure: The WP# protection status is latched only on the 6th write cycle of the embedded sector erase command sequence when the first sector is selected. If additional sectors are selected for erasure, they are subject to the WP# status that was latched on the 6th write cycle of the command sequence. Note that the WP# pin must not be left floating or unconnected; inconsistent behavior of the device may result. 8.22 Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control inputs to prevent unintentional writes when VCC is greater than VLKO. 8.23 Write Pulse "Glitch" Protection Noise pulses of less than tWEP on WE# do not initiate a write cycle. 8.24 Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. 26 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 8.24.1 Power-Up Write Inhibit If WE# = CE# = RESET# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up 8.25 Lock Register The Lock Register consists of 3 bits. Each of these bits are non-volatile and read-only. DQ15-DQ3 are reserved and are undefined. Table 8.11 Lock Register DQ15-DQ3 Undefined DQ2 Password Protection Mode Lock Bit DQ1 Persistent Protection Mode Lock Bit DQ0 Secured Silicon Sector Protection Bit Note When the device lock register is programmed (PPB mode lock bit is programmed, password mode lock bit programmed, or the Secured Silicon lock bit is programmed) all DYBs revert to the power-on default state. 8.26 Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. 8.27 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enters this mode when addresses and clock remain stable for tACC + 20 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. 8.28 RESET#: Hardware Reset Input The RESET# input provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS, the standby current will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 19.5 on page 70 for the timing diagram. 8.28.1 VCC Power-up and Power-down Sequencing The device imposes no restrictions on VCC power-up or power-down sequencing. Asserting RESET# to VIL is required during the entire VCC power sequence until the respective supplies reach their operating voltages. Once VCC attains its operating voltage, de-assertion of RESET# to VIH is permitted. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 27 Data Sheet (Advance Information) 8.29 Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The outputs are placed in the high impedance state. 8.30 Secured Silicon Sector SectorFlash Memory Region The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 words in length. All reads outside of the 256 word address range will return non-valid data. The Factory Indicator Bit (DQ7) is used to indicate whether or not the Factory Secured Silicon Sector is locked when shipped from the factory. The Customer Indicator Bit (DQ6) is used to indicate whether or not the Customer Secured Silicon Sector is locked when shipped from the factory. The Factory Secured Silicon bits are permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN and customer code once the product is shipped to the field. Spansion offers the device with a Factory Secured Silicon Sector that is locked and a Customer Secured Silicon Sector that is either locked or is lockable. The Factory Secured Silicon Sector is always protected when shipped from the factory, and has the Factory Indicator Bit (DQ7) permanently set to a "1". The Customer Secured Silicon Sector is shipped unprotected, allowing customers to utilize that sector in any manner they choose. Once the Customer Secured Silicon Sector area is protected, the Customer Indicator Bit will be permanently set to "1." The system accesses the Secured Silicon Sector through a command sequence (see Enter/Exit Secured Silicon Sector Command Sequence on page 42). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by sector SA0 of the memory array. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. While Secured Silicon Sector access is enabled, Memory Array read access, program operations, and erase operations to all sectors other than SA0 are also available. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. 8.30.1 Factory Locked: Factor Secured Silicon Sector Programmed and Protected At the Factory In a factory sector locked device, the Factory Secured Silicon Sector is protected when the device is shipped from the factory. The Factory Secured Silicon Sector cannot be modified in any way. The device is pre programmed with both a random number and a secure ESN. The Factory Secured Silicon Sector is located at addresses 000000h-00007Fh. The device is available pre programmed with one of the following: A random, secure ESN only within the Factor Secured Silicon Sector Customer code within the Customer Secured Silicon Sector through the SpansionTM programming services Both a random, secure ESN and customer code through the SpansionTM programming services. Table 8.12 Secured Silicon SectorSecure Sector Addresses Sector Customer Factory Sector Size 128 words 128 words Address Range 000080h-0000FFh 000000h-00007Fh Customers may opt to have their code programmed by Spansion through the SpansionTM programming services. Spansion programs the customer's code, with or without the random ESN. The devices are then shipped from Spansion's factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact an Spansion representative for details on using Spansion's SpansionTM programming services. 28 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 8.30.2 Customer Secured Silicon Sector If the security feature is not required, the Customer Secured Silicon SectorSecure Sector can be treated as an additional Flash memory space. The Customer Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Customer Secured Silicon Sector, but reading the first Bank through the last bank is available. The Customer Secured Silicon Sector is located at addresses 000080h-0000FFh. The Customer Secured Silicon Sector area can be protected by writing the Secured Silicon Sector Protection Bit Lock command sequence. Once the Customer Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing SA0 in the memory array. The Customer Secured Silicon Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the Customer Secured Silicon Sector area and none of the bits in the Customer Secured Silicon Sector memory space can be modified in any way. 9. Common Flash Memory Interface (CFI) The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 9.1-9.5. To terminate reading CFI data, the system must write the reset command. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact the local sales representative for copies of these documents. Table 9.1 CFI Query Identification String Data Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah S29NS256N S29NS128N 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h S29NS064N Description Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 29 Data Sheet (Advance Information) Table 9.2 System Interface String Data Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h S29NS256N S29NS128N 0017h 0019h 0000h 0000h 0006h 0009h 000Ah 0000h 0003h 0001h 0002h 0000h S29NS064N Description VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt ACC Min. voltage (00h = no ACC pin present) Refer to 4Dh ACC Max. voltage (00h = no ACC pin present) Refer to 4Eh Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) Table 9.3 Device Geometry Definition Data Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 00FEh 0000h 0000h 0002h 0003h 0000h 0080h 0000h 0000h 0000h Erase Block Region 3 Information 0000h 0000h 0000h 0000h Erase Block Region 4 Information 0000h 0000h S29NS256N 0019h 0001h Flash Device Interface description (refer to CFI publication 100) 0000h 0006h Max. number of bytes in multi-byte write = 2N (00h = not supported) 0000h 0002h 007Eh 0000h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h Erase Block Region 2 Information 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) Number of Erase Block Regions within device S29NS128N 0018h S29NS064N 0017h Device Size = 2N byte Description 30 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Table 9.4 Primary Vendor-Specific Extended Query Data Addresses 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0013h 00F0h S29NS256N S29NS128N 0050h 0052h 0049h 0031h 0034h 0010h 0002h 0001h 0000h 0008h 0078h 0001h 0000h 0085h 0095h 0003h 0001h 0001h 0008h 0008h 0008h 0005h 0005h 0010h 0008h 0008h 0008h 0008h 0008h 0008h 0008h 0008h 0008h 0008h 0008h 0008h 0008h 0008h 0008h 000Bh 0002h 0008h 0010h 0010h 0010h 0010h 0010h 0010h 0010h 0013h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0070h Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2= To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 08 = Advanced Sector Protection Simultaneous Operation Number of Sectors in all banks except boot bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode 00 = Not Supported, 01 = Supported ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3D0: 100 mv ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3D0: 100 mv Top/Bottom Boot Sector Flag 0001h = Top/Middle Boot Device, 0002h = Bottom Boot Device, 03h = Top Boot Device Program Suspend. 00h = not supported Unlock Bypass 00 = Not Supported, 01 = Supported Secured Silicon Sector (Customer OTP Area) Size 2N bytes Hardware Reset Low Time-out during an embedded algorithm to read more mode Maximum 2N ns Hardware Reset Low Time-out during an embedded algorithm to read more mode Maximum 2N ns Erase Suspend Time-out Maximum 2N ns Program Suspend Time-out Maximum 2N ns Bank Organization: X = Number of banks Bank 0 Region Information. X = Number of sectors in banks Bank 1 Region Information. X = Number of sectors in banks Bank 2 Region Information. X = Number of sectors in banks Bank 3 Region Information. X = Number of sectors in banks Bank 4 Region Information. X = Number of sectors in banks Bank 5 Region Information. X = Number of sectors in banks Bank 6 Region Information. X = Number of sectors in banks Bank 7 Region Information. X = Number of sectors in banks Bank 8 Region Information. X = Number of sectors in banks Bank 9 Region Information. X = Number of sectors in banks Bank 10 Region Information. X = Number of sectors in banks Bank 11 Region Information. X = Number of sectors in banks Bank 12 Region Information. X = Number of sectors in banks Bank 13 Region Information. X = Number of sectors in banks Bank 14 Region Information. X = Number of sectors in banks Bank 15 Region Information. X = Number of sectors in banks Process Technology. 00h = 230nm, 01h = 170nm, 02h = 130nm/110nm Query-unique ASCII string "PRI" S29NS064N Description S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 31 Data Sheet (Advance Information) Table 9.5 Sector Address Table, S29NS256N (Sheet 1 of 3) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 Bank 0 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 Bank 1 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Bank 4 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh Bank 6 Bank 3 Bank 2 Bank Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 32 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Table 9.5 Sector Address Table, S29NS256N (Sheet 2 of 3) Bank Sector SA80 SA81 SA82 SA83 SA84 SA85 SA86 Bank 5 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Bank 8 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 Bank 9 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 800000h-80FFFFh 810000h-81FFFFh 820000h-82FFFFh 830000h-83FFFFh 840000h-84FFFFh 850000h-85FFFFh 860000h-86FFFFh 870000h-87FFFFh 880000h-88FFFFh 890000h-89FFFFh 8A0000h-8AFFFFh 8B0000h-8BFFFFh 8C0000h-8CFFFFh 8D0000h-8DFFFFh 8E0000h-8EFFFFh 8F0000h-8FFFFFh 900000h-90FFFFh 910000h-91FFFFh 920000h-92FFFFh 930000h-93FFFFh 940000h-94FFFFh 950000h-95FFFFh 960000h-96FFFFh 970000h-97FFFFh 980000h-98FFFFh 990000h-99FFFFh 9A0000h-9AFFFFh 9B0000h-9BFFFFh 9C0000h-9CFFFFh 9D0000h-9DFFFFh 9E0000h-9EFFFFh 9F0000h-9FFFFFh Bank 11 Bank 10 Bank 7 Bank Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh A00000h-A0FFFFh A10000h-A1FFFFh A20000h-A2FFFFh A30000h-A3FFFFh A40000h-A4FFFFh A50000h-A5FFFFh A60000h-A6FFFFh A70000h-A7FFFFh A80000h-A8FFFFh A90000h-A9FFFFh AA0000h-AAFFFFh AB0000h-ABFFFFh AC0000h-ACFFFFh AD0000h-ADFFFFh AE0000h-AEFFFFh AF0000h-AFFFFFh B00000h-B0FFFFh B10000h-B1FFFFh B20000h-B2FFFFh B30000h-B3FFFFh B40000h-B4FFFFh B50000h-B5FFFFh B60000h-B6FFFFh B70000h-B7FFFFh B80000h-B8FFFFh B90000h-B9FFFFh BA0000h-BAFFFFh BB0000h-BBFFFFh BC0000h-BCFFFFh BD0000h-BDFFFFh BE0000h-BEFFFFh BF0000h-BFFFFFh S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 33 Data Sheet (Advance Information) Table 9.5 Sector Address Table, S29NS256N (Sheet 3 of 3) Bank Sector SA192 SA193 SA194 SA195 SA196 SA197 SA198 Bank 12 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 Bank 13 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range C00000h-C0FFFFh C10000h-C1FFFFh C20000h-C2FFFFh C30000h-C3FFFFh C40000h-C4FFFFh C50000h-C5FFFFh C60000h-C6FFFFh C70000h-C7FFFFh C80000h-C8FFFFh C90000h-C9FFFFh CA0000h-CAFFFFh CB0000h-CBFFFFh CC0000h-CCFFFFh CD0000h-CDFFFFh CE0000h-CEFFFFh CF0000h-CFFFFFh D00000h-D0FFFFh D10000h-D1FFFFh D20000h-D2FFFFh D30000h-D3FFFFh D40000h-D4FFFFh D50000h-D5FFFFh D60000h-D6FFFFh D70000h-D7FFFFh Bank 15 D80000h-D8FFFFh D90000h-D9FFFFh DA0000h-DAFFFFh DB0000h-DBFFFFh DC0000h-DCFFFFh DD0000h-DDFFFFh DE0000h-DEFFFFh DF0000h-DFFFFFh Bank 14 Bank Sector SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 16 K words 16 K words 16 K words 16 K words Address Range E00000h-E0FFFFh E10000h-E1FFFFh E20000h-E2FFFFh E30000h-E3FFFFh E40000h-E4FFFFh E50000h-E5FFFFh E60000h-E6FFFFh E70000h-E7FFFFh E80000h-E8FFFFh E90000h-E9FFFFh EA0000h-EAFFFFh EB0000h-EBFFFFh EC0000h-ECFFFFh ED0000h-EDFFFFh EE0000h-EEFFFFh EF0000h-EFFFFFh F00000h-F0FFFFh F10000h-F1FFFFh F20000h-F2FFFFh F30000h-F3FFFFh F40000h-F4FFFFh F50000h-F5FFFFh F60000h-F6FFFFh F70000h-F7FFFFh F80000h-F8FFFFh F90000h-F9FFFFh FA0000h-FAFFFFh FB0000h-FBFFFFh FC0000h-FCFFFFh FD0000h-FDFFFFh FE0000h-FEFFFFh FF0000h-FF3FFFh FF4000h-FF7FFFh FF8000h-FFBFFFh FFC000h-FFFFFFh 34 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Table 9.6 Sector Address Table, S29NS128N (Sheet 1 of 2) Bank Sector SA0 SA1 SA2 Bank 0 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 Bank 1 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 Bank 2 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 Bank 3 SA27 SA28 SA29 SA30 SA31 SA64 SA65 SA66 Bank 8 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 Bank 9 SA75 SA76 SA77 SA78 SA79 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh Bank 13 Bank 12 Bank 7 Bank 6 Bank 5 Bank 4 Bank Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words Address Range 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 35 Data Sheet (Advance Information) Table 9.6 Sector Address Table, S29NS128N (Sheet 2 of 2) Bank Sector SA80 SA81 SA82 Bank 10 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 Bank 11 SA91 SA92 SA93 SA94 SA95 Sector Size 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords 64 Kwords Address Range 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh Bank 15 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh Bank 14 Bank Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 Sector Size 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 64 K words 16 K words 16 K words 16 K words 16 K words Address Range 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7F3FFFh 7F4000h-7F7FFFh 7F8000h-7FBFFFh 7FC000h-7FFFFFh Table 9.7 Sector Address Table, S29NS064N (Sheet 1 of 3) Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 Bank 0 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Address Range 000000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-0F7FFFh Bank 2 Bank Sector SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Address Range 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 36 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Table 9.7 Sector Address Table, S29NS064N (Sheet 2 of 3) Bank Sector SA16 SA17 SA18 SA19 SA20 SA21 SA22 Bank 1 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA64 SA65 SA66 SA67 SA68 SA69 SA70 Bank 4 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Address Range 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-2F7FFFh Bank 6 Bank 3 Bank Sector SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Address Range 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 37 Data Sheet (Advance Information) Table 9.7 Sector Address Table, S29NS064N (Sheet 3 of 3) Bank Sector SA80 SA81 SA82 SA83 SA84 SA85 SA86 Bank 5 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Address Range 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh Bank 7 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh Bank Sector SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 Sector Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 8 Kwords 8 Kwords 8 Kwords 8 Kwords Address Range 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F9FFFh 3FA000h-3FBFFFh 3FC000h-3FDFFFh 3FE000h-3FFFFFh 10. Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. Table 11.4 on page 54 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the rising edge of AVD#. All data is latched on the rising edge of WE#. Refer to the AC Characteristics section for timing diagrams. 10.1 Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspendread mode, after which the system can read data from any non-erase-suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/Erase Resume Commands on page 48 for more information. After the device accepts a Program Suspend command, the corresponding bank enters the programsuspend-read mode, after which the system can read data from any non-program-suspended sector within the same bank. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See also VersatileIOTM (VIO) Control on page 16 and Requirements for Synchronous (Burst) Read Operation on page 17 in the Device Bus Operations section for more information. The Asynchronous Read and 38 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Synchronous/Burst Read tables provide the read parameters, and Figure 19.3 on page 68 and Figure 19.4 on page 69 show the timings. 10.2 Set Configuration Register Command Sequence The device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, RDY configuration, and synchronous mode active. The configuration register must be set before the device will enter burst mode. The configuration register is loaded with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be D0h and address bits should be 555h. During the fourth cycle, the configuration code should be entered onto the data bus with the address bus set to address 000h. Once the data has been programmed into the configuration register, a software reset command is required to set the device into the correct state. The device will power up or after a hardware reset with the default setting, which is in asynchronous mode. The register must be set before the device can enter synchronous mode. The configuration register can not be changed during device operations (program, erase, or sector lock). 10.3 Read Configuration Register Command Sequence The configuration register can be read with a four-cycle command sequence. The first two cycles are standard unlock sequences. On the third cycle, the data should be C6h and address bits should be 555h. During the fourth cycle, the configuration code should be read out of the data bus with the address bus set to address 000h. Once the data has been read from the configuration register, a software reset command is required to set the device into the correct set mode. 10.3.1 Read Mode Setting On power-up or hardware reset, the device is set to be in asynchronous read mode. This setting allows the system to enable or disable burst mode during system operations. 10.3.2 Programmable Wait State Configuration The programmable wait state feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Configuration Bit CR13-CR11 determine the setting (see Table 10.1). The wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. Table 10.1 Programmable Wait State Settings CR13 0 0 0 0 1 1 1 1 CR12 0 0 1 1 0 0 1 1 CR11 0 1 0 1 0 1 0 1 Total Initial Access Cycles 2 3 4 5 6 7 (default) Reserved Reserved Notes 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2. It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 39 Data Sheet (Advance Information) 10.3.3 Programmable Wait State The host system should set CR13-CR11 to 101/100/011 for a clock frequency of 66 MHz for the system/ device to execute at maximum speed. Table 10.2 describes the typical number of clock cycles (wait states) for various conditions. Table 10.2 Wait States for Handshaking Typical No. of Clock Cycles after AVD# Low Conditions at Address Initial address (VCCQ = 1.8 V) 66 MHz 6 10.3.4 Handshaking For optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. The autoselect function allows the host system to determine whether the flash device is enabled for handshaking. 10.3.5 Burst Length Configuration The device supports four different read modes: continuous mode, and 8, 16, and 32 word linear with or without wrap around modes. A continuous sequence (default) begins at the starting address and advances the address pointer until the burst operation is complete. If the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. For example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. The address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the starting location. The sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. Table 10.3 shows the CR2-CR0 and settings for the four read modes. Table 10.3 Burst Length Configuration Address Bits Burst Modes Continuous 8-word linear 16-word linear 32-word linear CR2 0 0 0 1 CR1 0 1 1 0 CR0 0 0 1 0 Notes 1. Upon power-up or hardware reset the default setting is continuous. 2. All other conditions are reserved. 10.3.6 Burst Wrap Around By default, the device will perform burst wrap around with CR3 set to a `1'. Changing the CR3 to a `0' disables burst wrap around. 10.3.7 RDY Configuration By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. CR8 determines this setting; "1" for RDY active (default) with data, "0" for RDY active one clock cycle before valid data. 40 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 10.3.8 RDY Polarity By default, the RDY pin will always indicate that the device is ready to handle a new transaction with CR10 set to a `1'. In this case, the RDY pin is active high. Changing the CR10 to a `0' sets the RDY pin to be active low. In this case, the RDY pin will always indicate that the device is ready to handle a new transaction when low. 11. Configuration Register Table 11.1 shows the address bits that determine the configuration register settings for various device functions. Table 11.1 Configuration Register CR BIt CR15 CR14 CR13 CR12 Function Reserved Reserved 0 = Default 0 = Default 000 = Data is valid on the 2nd active CLK edge after AVD# transition to VIH 001 = Data is valid on the 3rd active CLK edge after AVD# transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH 011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH 101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default) 110 = Reserved 111 = Reserved 0 = RDY signal is active low 1 = RDY signal is active high (default) 1 = Default 0 = RDY active one clock cycle before data 1 = RDY active with data (default) 1 = default 1 = default 0 = default 0 = default 0 = No Wrap Around Burst 1 = Wrap Around Burst (default) 000 = Continuous (default) 010 = 8-Word Linear Burst 011 = 16-Word Linear Burst 100 = 32-Word Linear Burst (All other bit settings are reserved) Settings (Binary) Programmable Wait State CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 RDY Polarity Reserved RDY Reserved Reserved Reserved Reserved Burst Wrap Around Burst Length Notes 1. Device will be in the default state upon power-up or hardware reset. 2. CR3 will always equal to 1 (Wrap around mode) when CR0,CR1,CR2 = 000 (continuous Burst mode). 3. A software reset command is required after a read or write command. 11.1 Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 41 Data Sheet (Advance Information) The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Note: If DQ1 goes high during a Write Buffer Programming operation, the system must write the "Write to Buffer Abort Reset" command sequence to RESET the device to reading array data. The standard RESET command will not work. See Table 11.4 on page 52 for details on this command sequence. 11.2 Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 11.4 on page 54 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. Autoselect does not support simultaneous operations or burst mode. Table 11.2 Device ID Read Data Description Manufacturer ID Device ID, Word 1 Device ID, Word 2 Device ID, Word 3 Revision ID Sector Block Lock/Unlock Address (BA) + 00h (BA) + 01h (BA) + 0Eh (BA) + 0Fh (BA) + 03h (SA) = 02h 256N 0001h 2D7E 2D2F 2D00 128N 0001h 2C7Eh 2C35h 2C00h TBD 0001 - Locked 0000 - Unlocked DQ15 - DQ8 = Reserved DQ7 - Factory Lock Bit 1 = Locked, 0 = Not Locked DQ6 - Customer Lock Bit 1 = Locked, 0 = Not Locked DQ5 Handshake Bit 1 = Reserved 0 = Standard Handshake DQ4 & DQ3 - WP# Protections Boot Code 01 = WP# Protects only the Top Boot Sectors DQ2-DQ0 = Reserved 064N 0001h 2B7Eh 2B33h 2B00h Indicator Bits (BA) + 07h The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. The following table describes the address requirements for the various autoselect functions, and the resulting data. BA represents the bank address. The device ID is read in three cycles. During this time, other banks are still available to read the data from the memory. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). 11.3 Enter/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 11.4 on page 54 shows the address and data requirements for both command sequences. 42 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 11.3.1 Unlock Bypass Command Sequence The unlock bypass feature allows the system to program faster than the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. During the unlock bypass mode only the command is valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. 11.4 Program Command Sequence Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 11.4 on page 54 shows the address and data requirements for the program command sequence. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by monitoring DQ7 or DQ6/DQ2. Refer to the Write Operation Status on page 57 for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may causes that bank to set DQ5 = 1 (change-up condition). However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." 11.4.1 11.4.2 Program Command Sequence (Unlock Bypass Mode) Once the device enters the unlock bypass mode, then a two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 11.4 on page 54 shows the requirements for the unlock bypass command sequences. 11.5 Accelerated Program The device offers accelerated program operations through the ACC input. When the system asserts ACC on this input, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the ACC input to accelerate the operation. Figure 11.1 illustrates the algorithm for the program operation. Refer to Table 19.5, Erase/Program Operations on page 71 and Figure 19.6 on page 72 for timing diagrams. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 43 Data Sheet (Advance Information) Figure 11.1 Program Operation START Write Program Command Sequence Embedded Program algorithm in progress Data Poll from System Verify Data? No Yes No Increment Address Last Address? Yes Programming Completed Note See Table 11.4 on page 54 for program. 44 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 11.6 Write Buffer Programming Command Sequence Write Buffer Programming Sequence allows for faster programming as compared to the standard Program Command Sequence. See Table 11.3 on page 45 for the program command sequence. Table 11.3 Write Buffer Command Sequence Sequence Unlock Command 1 Unlock Command 2 Write Buffer Load Specify the Number of Program Locations Load 1st data word Load next data word ... Load last data word Write Buffer Program Confirm Device goes busy Status monitoring through DQ pins (Perform Data Bar Polling on the Last Loaded Address) Note Write buffer addresses must be loaded in sequential order. Address 555 2AA Starting Address Starting Address Starting Address Write Buffer Location ... Write Buffer Location Sector Address Data 00AA 0055 0025h Word Count Program Data Program Data ... Program Data 0029h Number of locations to program minus 1 All addresses must be within write-buffer-page boundaries, but do not have to be loaded in any order Same as above Same as above Same as above This command must follow the last write buffer location loaded, or the operation will ABORT Comment Not required in the Unlock Bypass mode Same as above S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 45 Data Sheet (Advance Information) Figure 11.2 Write Buffer Programming Operation Write "Write to Buffer" command and Sector Address Write number of addresses to program minus 1(WC) and Sector Address Part of "Write to Buffer" Command Sequence Write first address/data Yes WC = 0 ? No Abort Write to Buffer Operation? No Write next address/data pair Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write to a different sector address WC = WC - 1 Write program buffer to flash sector address Read DQ15 - DQ0 at Last Loaded Address DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? Yes Read DQ15 - DQ0 with address = Last Loaded Address No Yes DQ7 = Data? No FAIL or ABORT Yes PASS 11.7 Chip Erase Command Sequence Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 11.4 on page 54 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6/DQ2. Refer to Write Operation Status on page 57 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. 11.7.1 46 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 11.8 Sector Erase Command Sequence Sector Erase Command Sequence Sector erase in normal mode is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 11.4 on page 54 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of no less than tSEA, sector erase accept, occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than tSEA. Any sector erase address and command following the exceeded time-out may or may not be accepted. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase start timeout state indicator.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing banks. The system can determine the status of the erase operation by reading DQ7 or DQ6/ DQ2 in the erasing bank. Refer to Write Operation Status on page 57 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. 11.8.1 11.8.2 Accelerated Sector Erase The device offers accelerated sector erase operation through the ACC function. This method of erasing sectors is faster than the standard sector erase command sequence. The accelerated sector erase function must not be used more than 100 times per sector. In addition, accelerated sector erase should be performed at room temperature (30C +-10C). The following procedure is used to perform accelerated sector erase: 1. Sectors to be erased must be PPB and DYB cleared. All sectors that remain locked will not be erased. 2. Apply 9V to the ACC input. This voltage must be applied at least 1 s before executing step 3 3. Issue the standard chip erase command. 4. Monitor status bits DQ2/DQ6 or DQ7 to determine when erasure is complete, just as in the standard erase operation. See Write Operation Status on page 57 for further details. 5. Lower ACC from 9V to VCC. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 47 Data Sheet (Advance Information) Figure 11.3 Erase Operation START Write Erase Command Sequence Data Poll from System Embedded Erase algorithm in progress No Data = FFh? Yes Erasure Completed Note See the section on DQ3 for information on the sector erase start timeout state indicator. 11.9 Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, program data to, any sector not selected for erasure. The system may also lock or unlock any sector while the erase operation is suspended. The system must not write the sector lock/unlock command to sectors selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the minimum tSEA time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of tESL, erase suspend latency, to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) The system may also lock or unlock any sector while in the erase-suspend-read mode. Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erasesuspended. Refer to Write Operation Status on page 57 for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. Refer to Write Operation Status on page 57 for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Functions and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Note: While an erase operation can be suspended and resumed multiple times, a minimum delay of tERS (Erase Resume to Erase Suspend) is required from resume to the next suspend. 48 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 11.10 Program Suspend/Program Resume Commands The Program Suspend command allows the system to interrupt a embedded programming operation or a "Write to Buffer" programming operation so that data can read from any non-suspended sector. When the Program Suspend command is written during a programming process, the device halts the programming operation within tPSL, program suspend latency, and updates the status bits. Addresses are defined when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any nonsuspended sector. The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Secured Silicon Sector area (One Time Program area), then user must use the proper command sequences to enter and exit this region. The system may also write the autoselect command sequence when the device is in Program Suspend mode. The device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to Program Suspend mode, and is ready for another valid operation. See "Autoselect Command Sequence" for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See "Write Operation Status" for more information. The system must write the Program Resume command (address bits are "don't care") to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resume programming. Note: While a program operation can be suspended and resumed multiple times, a minimum delay of tPRS (Program Resume to Program Suspend) is required from resume to the next suspend. 11.11 Lock Register Command Set Definitions The Lock Register Command Set permits the user to one-time program the Persistent Protection Mode Lock Bit or Password Protection Mode Lock Bit. The Lock Command Set also allows for the reading of the Persistent Protection Mode Lock Bit or Password Protection Mode Lock Bit. The Lock Register Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Lock Register Command Set Entry command disables reads and writes for Bank 0. Reads from other banks excluding Bank 0 are allowed. Lock Register Program Command Lock Register Read Command Lock Register Exit Command The Lock Register Command Set Exit command must be issued after the execution of the commands to reset the device to read mode, and re-enables reads and writes for Bank 0. For the device to be permanently set to the Persistent Protection Mode or the Password Protection Mode, the sequence of a Lock Register Command Set Exit command, must be initiated after issuing the Persistent Protection Mode Lock Bit Program and the Password Protection Mode Lock Bit Program commands. Note that if the Persistent Protection Mode Lock Bit and the Password Protection Mode Lock Bit are programmed at the same time, neither will be programmed. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 49 Data Sheet (Advance Information) 11.12 Password Protection Command Set Definitions The Password Protection Command Set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. The Password Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Password Protection Command Set Entry command disables reads and writes for Bank 0. Reads for other banks excluding Bank 0 are allowed. However Writes to any bank are not allowed. Password Program Command Password Read Command Password Unlock Command The Password Program Command permits programming the password that is used as part of the hardware protection scheme. The actual password is 64-bits long. There is no special addressing order required for programming the password. Once the Password is written and verified, the Password Mode Locking Bit must be set in order to prevent verification. The Password Program Command is only capable of programming "0"s. Programming a "1" after a cell is programmed as a "0" results in a time-out by the Embedded Program Algorithm with the cell remaining as a "0". The password is all 1's when shipped from the factory. All 64-bit password combinations are valid as a password. The Password Verify Command is used to verify the Password. The Password is verifiable only when the Password Mode Lock Bit is not programmed. If the Password Mode Lock Bit is programmed and the user attempts to verify the Password, the device will always drive all 1's onto the DQ data bus. The lower two address bits (A1-A0) are valid during the Password Read, Password Program, and Password Unlock. The Password Unlock command is used to clear the PPB Lock Bit so that the PPBs can be unlocked for modification, thereby allowing the PPBs to become accessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than 1 s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. If the command is issued before the 1 s execution window for each portion of the unlock, the command will be ignored. The Password Unlock function is accomplished by writing Password Unlock command and data to the device to perform the clearing of the PPB Lock Bit. The password is 64 bits long. A1 and A0 are used for matching. Writing the Password Unlock command does not need to be address order specific. An example sequence is starting with the lower address A1-A0= 00, followed by A1-A0= 01, A1-A0= 10, and A1-A0= 11. Approximately 1 s is required for unlocking the device after the valid 64-bit password is given to the device. It is the responsibility of the microprocessor to keep track of the entering the portions of the 64-bit password with the Password Unlock command, the order, and when to read the PPB Lock bit to confirm successful password unlock. In order to re-lock the device into the Password Mode, the PPB Lock Bit Set command can be re-issued. The Password Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode, otherwise the device will hang. Note that issuing the Password Protection Command Set Exit command re-enables reads and writes for Bank 0. 50 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 11.13 Non-Volatile Sector Protection Command Set Definitions The Non-Volatile Sector Protection Command Set permits the user to program the Persistent Protection Bits (PPBs), erase all of the Persistent Protection Bits (PPBs), and read the logic state of the Persistent Protection Bits (PPBs). The Non-Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Non-Volatile Sector Protection Command Set Entry command disables reads and writes for Active Bank. Reads from other banks excluding Active Bank are allowed. PPB Program Command All PPB Erase Command PPB Status Read Command The PPB Program command is used to program, or set, a given PPB. Each PPB is individually programmed (but is bulk erased with the other PPBs). The specific sector addresses (AMAX-A14) are written at the same time as the program command. If the PPB Lock Bit is set, the PPB Program command will not execute and the command will time-out without programming the PPB. The All PPB Erase command is used to erase all PPBs in bulk. There is no means for individually erasing a specific PPB. Unlike the PPB program, no specific sector address is required. However, when the PPB erase command is written, all Sector PPBs are erased in parallel. If the PPB Lock Bit is set the ALL PPB Erase command will not execute and the command will time-out without erasing the PPBs. The device will preprogram all PPBs prior to erasing when issuing the All PPB Erase command. Also note that the total number of PPB program/erase cycles has the same endurance as the flash memory array. The programming state of the PPB for a given sector can be verified by writing a PPB Status Read Command to the device. See Table 11.4 on page 52 for the PPB program/erase algorithm. Note: PPB reads data only asynchronously. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 51 Data Sheet (Advance Information) Figure 11.4 PPB Program/Erase Algorithm Enter PPB Command Set. Addr = BA Program PPB Bit. Addr = SA Read Byte. Addr = SA0 Read Byte. Addr = SA0 DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte Twice. Addr = SA0 DQ6 = Toggle? Yes No Read Byte. Addr = SA No DQ0 = '1' (Erase) '0' (Pgm.)? Yes FAIL Issue Reset Command PASS Exit PPB Command Set Note The bank entered during entry is the active bank. Take for example the active bank is BA0. Any reads in BA0 will result in status reads of the PPB bit. If the user wants to set (programmed to "0") in a different bank other than the active bank, say for example BA5, then the active bank switches from BA0 to BA5. Reading in BA5 will result in status read of the bit whereas reading in BA0 will result in true data. 52 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) The Non-Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Note that issuing the Non-Volatile Sector Protection Command Set Exit command re-enables reads and writes for Active Bank. After entering the PPB Mode The PPB Status Read (BA) is the Mode entry (BA) If PPB Program command is given, the new PPB Status Read (BA) will be the same (BA) as given in the PPB Program. If PPB Erase command is given, the new PPB Status Read (BA) is the same (BA) as given in the PPB Program or PPB Set Entry, whichever was last. During PPB Program or Erase Operation, PPB status read is not available. Only polling data is available in Bank0 and no other bank. Reading from all other banks will give core data. 11.14 Global Volatile Sector Protection Freeze Command Set The Global Volatile Sector Protection Freeze Command Set permits the user to set the PPB Lock Bit and reading the logic state of the PPB Lock Bit. The Volatile Sector Protection Freeze Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Reads from all banks excluding mode entry bank are allowed. PPB Lock Bit Set Command PPB Lock Bit Status Read Command The PPB Lock Bit Set command is used to set the PPB Lock bit if it is cleared either at reset or if the Password Unlock command was successfully executed. There is no PPB Lock Bit Clear command. Once the PPB Lock Bit is set, it cannot be cleared unless the device is taken through a power-on clear (for Persistent Sector Protection Mode) or the Password Unlock command is executed (for Password Sector Protection Mode). If the Password Mode Locking Bit is set, the PPB Lock Bit status is reflected as set, even after a power-on reset cycle. The programming state of the PPB Lock Bit can be verified by executing a PPB Lock Bit Status Read Command to the device. The Global Volatile Sector Protection Freeze Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. 11.15 Volatile Sector Protection Command Set The Volatile Sector Protection Command Set permits the user to set the Dynamic Protection Bit (DYB), clear the Dynamic Protection Bit (DYB), and read the logic state of the Dynamic Protection Bit (DYB). The Volatile Sector Protection Command Set Entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. Note that issuing the Volatile Sector Protection Command Set Entry command disables reads and writes for the bank selected with the command. Reads for other banks excluding the selected bank are allowed. DYB Set Command DYB Clear Command DYB Status Read Command The DYB Set/Clear command is used to set or clear a DYB for a given sector. The high order address bits (A23-A14 for the NS256N, A22-A14 for the NS128N and A21-A14 for the NS064N) are issued at the same time as the code 00h or 01h on DQ7-DQ0. All other DQ data bus pins are ignored during the data write cycle. The DYBs are modifiable at any time, regardless of the state of the PPB or PPB Lock Bit. The DYBs are set at power-up or hardware reset. The programming state of the DYB for a given sector can be verified by writing a DYB Status Read Command to the device. Note that DYB reads data only asynchronously. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 53 Data Sheet (Advance Information) Note: The bank entered during entry is the active bank. Take for example the active bank is BA0. Any reads in BA0 will result in status reads of the DYB bit. If the user wants to set (programmed to "0") in a different bank other than the active bank, say for example BA5, then the active bank switches from BA0 to BA5. Reading in BA5 will result in status read of the bit whereas reading in BA0 will result in true data. The Volatile Sector Protection Command Set Exit command must be issued after the execution of the commands listed previously to reset the device to read mode. Note that issuing the Volatile Sector Protection Command Set Exit command re-enables reads and writes for the bank selected. Table 11.4 Command Definitions (Sheet 1 of 3) Bus Cycles (Notes 1-6) Cycles First Addr 1 1 4 RA XXX 555 Data RD F0 AA 2AA 55 (BA) 555 (BA) 555 (BA) 555 (BA) 555 555 90 (BA) X00 (BA) X01 (BA) X0D (BA) X03 0001 (Note 10) (Note 11) (BA) X0E (Note 10) (BA) X0F (Note 10) Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Seventh Addr Data Command Sequence (Notes) Asynchronous Read (7) Reset (8) Manufacturer ID Autoselect (9) Device ID 6 555 AA 2AA 55 90 Indicator Bits (11) 4 555 AA 2AA 55 90 Revision ID Unlock Bypass Mode Entry Program (12) Reset (13) 4 3 2 2 1 4 6 1 3 6 6 1 555 555 XXX BA 55 555 555 SA 555 555 555 BA AA AA A0 90 98 AA AA 29 AA AA AA B0 2AA 2AA PA XXX 55 55 PD 00 90 20 CFI Program Write to Buffer (17) Program Buffer to Flash Write to Buffer Abort Reset (20) Chip Erase Sector Erase Erase Suspend / Program Suspend (14) Erase Resume / Program Resume (15) Set Config. Register (28) 2AA 2AA 55 55 555 SA A0 25 PA SA PD WC PA PD WBL PD 2AA 2AA 2AA 55 55 55 555 555 555 F0 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 1 BA 30 4 555 AA 2AA 55 555 D0 X00 CR Read Configuration Register 4 555 AA 2AA 55 555 C6 X00 CR 54 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Table 11.4 Command Definitions (Sheet 2 of 3) Bus Cycles (Notes 1-6) Cycles First Addr Data Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Seventh Addr Data Command Sequence (Notes) Lock Register Command Set Definitions Lock Register Command Set Entry Lock Register Bits Program (23) Lock Register Bits Read Lock Register Command Set Exit (24) 3 555 AA 2AA 55 555 40 2 XX (BA0) 00 XX A0 00 data Lock 1 data 2 90 XX 00 Password Protection Command Set Definitions Password Protection Command Set Entry 3 555 AA 2AA 55 PWD0 / PWD1 / PWD2 / PWD3 PWD1 02 PWD2 03 PWD3 555 60 Password Program (24, 26) Pass-word 2 XX A0 00/ 01/ 02/ 03 Password Read (27) Password Unlock (26) Password Protection Command Set Exit 4 00 PWD 0 01 7 00 25 00 03 00 PWD0 01 PWD1 02 PWD2 03 PWD3 00 29 2 XX 90 XX 00 Non-Volatile Sector Protection Command Set Definitions Non-Volatile Sector Protection Command Set Entry PPB Program (29) PPB All PPB Erase (19, 29) PPB Status Read Non-Volatile Sector Protection Command Set Exit (BA) 555 3 555 AA 2AA 55 C0 2 2 1 XX XX (BA) SA A0 80 RD (0) (BA) SA SA0 00 30 2 XX 90 XX 00 Global Volatile Sector Protection Command Set Definitions Global Volatile Sector Protection Freeze Command Set Entry PPB Lock Bit PPB Lock Bit Set PPB Lock Bit Status Read Global Volatile Sector Protection Freeze Command Set Exit (BA) 555 3 555 AA 2AA 55 50 2 1 XX (BA)X X A0 RD (0) XX 00 2 XX 90 XX 00 S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 55 Data Sheet (Advance Information) Table 11.4 Command Definitions (Sheet 3 of 3) Bus Cycles (Notes 1-6) Cycles First Addr Data Second Addr Data Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data Seventh Addr Data Command Sequence (Notes) Secured Silicon Sector Command Definitions Secured Silicon Sector Entry (21) Secured Silicon Sector Program Secured Silicon Sector Read Secured Silicon Sector Exit (24) 3 555 AA 2AA 55 555 88 Secured Silicon Sector 2 XX A0 00 data 1 00 data 4 555 AA 2AA 55 555 90 XX 00 Volatile Sector Protection Command Set Definitions Volatile Sector Protection Command Set Entry (21) DYB Set DYB 3 555 AA 2AA (BA) SA (BA) SA 55 (BA) 555 E0 2 XX A0 00 DYB Clear 2 XX (BA) SA XX A0 01 DYB Status Read Volatile Sector Protection Command Set Exit (24) Legend X = Don't care 1 RD(0) 2 90 XX 00 RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0]. PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must be set to `0' for protection while PD(2), bit[2] must be left as `1'. PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must be set to `0' for protection while PD(1), bit[1] must be left as `1'. PD(3) = Protection Mode OTP Bit. PD(3) or bit[3]. SA = Address of the sector to be verified (in autoselect mode) or erased. SA includes BA. Address bits Amax-A14 uniquely select any sector (NS256N and NS128N), and address bits Amax - A13 uniquely select any sector (NS064N). BA = Address of the bank (A23-A20 for S29NS256N, A22-A19 for S29NS128N), and A21-A19 for S29NS064N, that is being switched to autoselect mode, is in bypass mode, or is being erased. CR = Configuration Register set by data bits D15-D0. PWD3-PWD0 = Password Data. PD3-PD0 present four 16 bit combinations that represent the 64-bit Password PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1. RD(1) = DQ1 protection indicator bit. If protected, DQ1 = 0, if unprotected, DQ1 = 1. RD(2) = DQ2 protection indicator bit. If protected, DQ2 = 0, if unprotected, DQ2 = 1. RD(4) = DQ4 protection indicator bit. If protected, DQ4 = 0, if unprotected, DQ4 = 1. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes 1. See Table 8.1 on page 16 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15-DQ8 are don't care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits Amax-A12 are don't cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 56 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). 9. The fourth cycle of the autoselect command sequence is a read cycle. The system must read device IDs across the 4th, 5th, and 6th cycles, The system must provide the bank address. See the Autoselect Command Sequence section for more information. 10. See Table 11.2 on page 42 for description of bus operations. 11. See the Autoselect Command Sequence on page 42. 12. The Unlock Bypass command sequence is required prior to this command sequence. 13. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 15. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 16. Command is valid when device is ready to read array data or when device is in autoselect mode. 17. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 18. The entire four bus-cycle sequence must be entered for which portion of the password. 19. The ALL PPB ERASE command will pre-program all PPBs before erasure to prevent over-erasure of PPBs. 20. Command sequence resets device for next command after write-to-buffer operation. 21. Entry commands are needed to enter a specific mode to enable instructions only available within that mode. 22. Write Buffer Programming can be initiated after Unlock Bypass Entry. 23. If both the Persistent Protection Mode Locking Bit and the password Protection Mode Locking Bit are set a the same time, the command operation will abort and return the device to the default Persistent Sector Protection Mode. 24. The Exit command must be issued to reset the device into read mode. Otherwise the device will hang. 25. Note: Autoselect, CFI, OTP, Unlock Bypass Mode and all ASP modes cannot be nested with each other. 26. Only A7 - A0 (lower address bits) are used 27. Amax-A0 (all address bits) are used. 28. Requires the RESET# command to configure the configuration register. 29. See Figure 11.4 on page 52 for details. 12. Write Operation Status The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12.2 on page 62 and the following subsections describe the function of these bits. DQ7 and DQ6 each offers a method for determining whether a program or erase operation is complete or in progress. 12.1 DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling status on any word other than the last word to be programmed in the write-buffer-page will return false status information. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately tPSP, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately tASP, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 57 Data Sheet (Advance Information) Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ6-DQ0 may be still invalid. Valid data on DQ7-DQ0 will appear on successive read cycles. Table 12.2 on page 62 shows the outputs for Data# Polling on DQ7. Figure 12.1 on page 58 shows the Data# Polling algorithm. Figure 19.9 on page 74 in the AC Characteristics section shows the Data# Polling timing diagram. Figure 12.1 Data# Polling Algorithm START Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read DQ7-DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5. 58 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 12.2 RDY: Ready The RDY pin is a dedicated status output that indicates valid output data on A/DQ15-A/DQ0 during burst (synchronous) reads. When RDY is asserted (RDY = VOH), the output data is valid and can be read. When RDY is de-asserted (RDY = VOL), the system should wait until RDY is re-asserted before expecting the next word of data. In synchronous (burst) mode with CE# = OE# = VIL, RDY is de-asserted under the following conditions: during the initial access; after crossing the internal boundary between addresses 7Eh and 7Fh (and addresses offset from these by a multiple of 64). The RDY pin will also switch during status reads when a clock signal drives the CLK input. In addition, RDY = VOH when CE# = VIL and OE# = VIH, and RDY is Hi-Z when CE# = VIH. In asynchronous (non-burst) mode, the RDY pin does not indicate valid or invalid output data. Instead, RDY = VOH when CE# = VIL, and RDY is Hi-Z when CE# = VIH. 12.3 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address in the same bank, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. Note that OE# must be low during toggle bit status reads. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately tASP, all sectors protected toggle time, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling on page 57). If a program address falls within a protected sector, DQ6 toggles for approximately tPSP after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. See the following for additional information: (toggle bit flowchart), DQ6: Toggle Bit I on page 59 (description), Figure 19.10 on page 75 (toggle bit timing diagram), and Table 12.1 on page 61 (compares DQ2 and DQ6). 12.4 DQ2: Toggle Bit II The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. Note that OE# must be low during toggle bit status reads. But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 12.2 on page 62 to compare outputs for DQ2 and DQ6. See the following for additional information: (toggle bit flowchart), DQ6: Toggle Bit I on page 59 (description), Figure 19.10 on page 75 (toggle bit timing diagram), and Table 12.1 on page 61 (compares DQ2 and DQ6). S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 59 Data Sheet (Advance Information) Figure 12.2 Toggle Bit Algorithm START Read Byte DQ7-DQ0 Address = VA Read Byte DQ7-DQ0 Address = VA DQ6 = Toggle? Yes No No DQ5 = 1? Yes Read Byte Twice DQ7-DQ0 Adrdess = VA DQ6 = Toggle? No Yes FAIL PASS Note The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information. 60 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Table 12.1 DQ6 and DQ2 Indications If device is programming, and the system reads at any address, at an address within a sector selected for erasure, actively erasing, at an address within sectors not selected for erasure, at an address within a sector selected for erasure, erase suspended, at an address within sectors not selected for erasure, programming in erase suspend at any address, returns array data, toggles, returns array data. The system can read from any sector not selected for erasure. is not applicable. toggles, does not toggle, does not toggle. toggles. then DQ6 toggles, toggles, and DQ2 does not toggle. also toggles. 12.5 Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. 12.6 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). 12.7 DQ3: Sector Erase Start Timeout State Indicator After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than tSEA, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 61 Data Sheet (Advance Information) To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 12.2 on page 62 shows the status of DQ3 relative to the other status bits. 12.8 DQ1: Write to Buffer Abort DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a `1'. The system must issue the Write to Buffer Abort Reset command sequence to return the device to reading array data. See Write Buffer Programming Operation on page 20 for more details. Table 12.2 Write Operation Status Status Standard Mode Program Suspend Mode (Note 3) Embedded Program Algorithm Embedded Erase Algorithm Reading within Program Suspended Sector Reading within Non-Program Suspended Sector Erase-SuspendRead Erase Suspended Sector Non-Erase Suspended Sector 1 Data DQ7# DQ7# DQ7# DQ7# No toggle Data Toggle Toggle Toggle Toggle 0 Data 0 0 1 0 DQ7 (Note 2) DQ7# 0 DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 (Note 4) 0 N/A Valid data for all address except the address being programed, which will return invalid data Data N/A Data N/A N/A N/A N/A Toggle Data N/A N/A N/A N/A N/A Data N/A 0 0 1 Erase Suspend Mode Erase-Suspend-Program Write to Buffer (Note 5) BUSY State Exceeded Timing Limits ABORT State Notes 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. Data are invalid for addresses in a Program Suspended sector. 4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations. 5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location. 62 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 13. Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Voltage with Respect to Ground, All Inputs and I/Os except ACC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +2.5 V ACC (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to + 9.5 V Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Notes 1. Minimum DC voltage on input or I/Os is -0.5 V. During voltage transitions, input at I/Os may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 13.1 on page 63. Maximum DC voltage on input and I/Os is VCC + 0.5 V. During voltage transitions outputs may overshoot to VCC + 2.0 V for periods up to 20 ns. See Figure 13.2 on page 63. 2. Minimum DC input voltage on ACC is -0.5 V. During voltage transitions, ACC may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 13.1 on page 63. Maximum DC input voltage on ACC is +9.5 V which may overshoot to +10.5 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. Figure 13.1 Maximum Negative Overshoot Waveform 20 ns +0.8 V -0.5 V -2.0 V 20 ns 20 ns Figure 13.2 Maximum Positive Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 1.0 V 20 ns 20 ns 14. Operating Ranges Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-25C to +85C Ambient Temperature (TA) during Accelerated Sector Erase . . . . . . . . . . . . . . .+20C to +40C VCC Supply Voltages VCC min. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.70 V VCC max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.95 V Operating ranges define those limits between which the functionality of the device is guaranteed. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 63 Data Sheet (Advance Information) 15. DC Characteristics 15.1 CMOS Compatible Parameter ILI ILO Description Input Load Current Output Leakage Current Test Conditions (Note 1) VIN = VSS to VCC, VCC = VCC max VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIL, burst length = 8 CE# = VIL, OE# = VIL, burst ICCB VCC Active Burst Read Current (Note 5) length = 16 CE# = VIL, OE# = VIL, burst length = 32 CE# = VIL, OE# = VIL, burst length = continuous ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 IPPW IPPE VIL VIH VOL VOH VID VLKO VCC Active Asynchronous Read Current (Note 2) VCC Active Write Current (Note 3) VCC Standby Current (Note 4) VCC Reset Current VCC Active Current (Read While Write) VCC Sleep Current Accelerated Program Current (Note 6) Accelerated Erase Current (Note 6) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage IOL = 100 A, VCC = VCC min IOH = -100 A, VCC = VCC min VCCQ - 0.1 8.5 1.0 9.5 1.4 CE# = VIL, OE# = VIH 66 MHz 24 Min Typ Max 1 1 33 Unit A A mA 66 MHz 66 MHz 66 MHz 5 MHz 1 MHz 24 26 28 15 3 19 20 80 50 20 20 20 -0.5 VCCQ - 0.4 35 37 39 18 4 52.5 70 150 60 70 30 30 0.4 VCCQ + 0.2 0.1 mA mA mA mA mA mA A A mA A mA mA V V V V V V CE# = VIL, OE# = VIH, ACC = VIH CE# = VIH, RESET# = VIH (Note 8) RESET# = VIL, CLK = VIL (Note 8) CE# = VIL, OE# = VIL (Note 8) (Note 9) CE# = VIL, OE# = VIH ACC = 9 V ACC = 9 V Notes 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Device enters automatic sleep mode when addresses are stable for tACC + 20 ns. Typical sleep mode current is equal to ICC3. 5. Specifications assume 8 I/Os switching. 6. Not 100% tested. ACC is not a power supply pin. 7. While measuring Output Leakage Current, CE# should be at VIH. 8. VIH = VCC -0.2 V and VIL > -0.1V. 9. Clock Frequency 66 MHz and in Continuous Mode. 64 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 16. Test Conditions Figure 16.1 Test Setup Device Under Test CL Table 16.1 Test Specifications Test Condition Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels All Speeds 30 3 @ 66 MHz 0.0-VCC VCCQ/2 VCCQ/2 Unit pF ns V V V 17. Key to Switching Waveforms Waveform Inputs Steady Outputs Changing from H to L Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) 18. Switching Waveforms Figure 18.1 Input Waveforms and Measurement Levels VCCQ Input 0.0 V VCCQ/2 Measurement Level VCCQ/2 Output S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 65 Data Sheet (Advance Information) 19. AC Characteristics 19.1 VCC Power-up Parameter tVCS Notes 1. VCC >+ VCCQ - 100 mV 2. VCC ramp rate is >1 V/100 s Description VCC Setup Time Test Setup Min Speed 1 Unit ms Figure 19.1 VCC Power-up Diagram CLK Characterization tVCS VCC VCCQ RESET# Parameter fCLK tCLK tCH tCL tCR (Note) tCF (Note) Notes 1. Clock jitter of +/- 5% permitted. 2. Not 100% tested. Description CLK Frequency CLK Period CLK High Time Min CLK Low Time CLK Rise Time Max CLK Fall Time Max Min (66 MHz) 66 15.0 6.1 Unit MHz ns ns 3 ns Figure 19.2 CLK Characterization tCLK tCH tCL CLK tCR tCF 66 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 19.2 Synchronous/Burst Read Parameter JEDEC Standard tIACC tBACC tAVDS tAVDH tAVDO tACS tACH tBDH tOE tCEZ tOEZ tCES tRDYS tRACC Note Not 100% tested. Initial Access Time Burst Access Time Valid Clock to Output Delay AVD# Setup Time to CLK AVD# Hold Time from CLK AVD# High to OE# Low Address Setup Time to CLK Address Hold Time from CLK Data Hold Time from Next Clock Cycle Output Enable to Data, or RDY Valid Chip Enable to High Z (Note) Output Enable to High Z (Note) CE# Setup Time to CLK RDY Setup Time to CLK Ready access time from CLK Description Max Max Min Min Min Min Min Min Max Max Max Min Min Max (66 MHz) 80 11.0 4 6 0 4 6 3 11.0 10 10 4 4 11.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 67 Data Sheet (Advance Information) Figure 19.3 Burst Mode Read 5 cycles for initial access shown. tCES CE# 1 CLK tAVDS AVD# tACS Amax-A16 Aa 15.2 ns typ. (66 MHz) tCEZ 6 7 2 3 4 5 tAVDH tAVDO tACH A/DQ15A/DQ0 (n) Aa tBACC Hi-Z tIACC Da Da + 1 Da + 2 Da + 3 Da + n tBDH OE# tOE RDY (n) Hi-Z tOEZ tRACC Hi-Z tCR tRDYS Hi-Z Da Da + 1 Da + 2 Da + 2 Da + n A/DQ15A/DQ0 (n + 1) Hi-Z RDY (n + 1) Hi-Z A/DQ15A/DQ0 (n + 2) Hi-Z Hi-Z Da Da + 1 Da + 1 Da + 1 Da + n RDY (n + 2) Hi-Z A/DQ15A/DQ0 (n + 3) Hi-Z Hi-Z Da Da Da Da Da + n RDY (n + 3) Hi-Z Notes 1. Figure shows total number of clock set to five. 2. If any burst address occurs at "address + 1", "address + 2", or "address +3", additional clock delays are inserted, and are indicated by RDY. 68 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 19.3 Asynchronous Read Parameter JEDEC Standard tCE tACC tAVDP tAAVDS tAAVDH tOE tOEH tOEZ Note Not 100% tested. Access Time from CE# Low Asynchronous Access Time AVD# Low Time Address Setup Time to Rising Edge of AVD Address Hold Time from Rising Edge of AVD Output Enable to Output Valid Read Output Enable Hold Time Toggle and Data# Polling Output Enable to High Z (See Note) Min Max 10 10 ns ns Description Max Max Min Min Min Max Min (66 MHz) 80 80 8 4 3.7 11.0 0 Unit ns ns ns ns ns ns ns Figure 19.4 Asynchronous Mode Read CE# tOE tOEH WE# A/DQ15- A/DQ0 tCE RA tACC Amax-A16 RA tAAVDH AVD# tAVDP tAAVDS Note RA = Read Address, RD = Read Data. OE# tOEZ Valid RD S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 69 Data Sheet (Advance Information) 19.4 Hardware Reset (RESET#) Parameter JEDEC Std tRP tRH Note Not 100% tested Description RESET# Pulse Width Reset High Time Before Read Min Min All Speed Options 200 10 Unit ns s Figure 19.5 Reset Timings CE#, OE# tRH RESET# tRP 70 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 19.5 Erase/Program Operations Parameter JEDEC tAVAV tAVWL tWLAX Standard tWC tAS tAH tAVDP tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL tDS tDH tGHWL tCS tCH tWP/tWRL tWPH tSR/W tACC tVPS tVCS tSEA tESL tPSL tERS tPRS tPSP tASP tWEP Notes 1. Not 100% tested. 2. See the Erase and Programming Performance section for more information. 3. Does not include the preprogramming time. Write Cycle Time (Note 1) Address Setup Time Address Hold Time AVD# Low Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time to WE# CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations ACC Rise and Fall Time ACC Setup Time (During Accelerated Programming) VCC Setup Time Sector Erase Accept Time-out Erase Suspend Latency Program Suspend Latency Erase Resume to Erase Suspend Program Resume to Program Suspend Toggle Time During Programming Within a Protected Sector Toggle Time During Sector Protection Noise Pulse Margin on WE# Description Min Min Min Min Min Min Typ Typ Typ Typ Typ Min Min Min Min Max Max Max Min Min Typ Typ Max (66 MHz) 45 4 6 8 25 0 0 8 0 30 20 0 500 1 50 50 35 35 30 30 1 100 3 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s s s s s ns S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 71 Data Sheet (Advance Information) Figure 19.6 Program Operation Timings Program Command Sequence (last two cycles) tAS AVD tAH tAVDP Amax-A16 PA VA In Progress Read Status Data VA A/DQ15- A/DQ0 CE# 555h A0h PA PD tDS tDH VA VA Complete OE# tWP WE# tCS tCH tWHWH1 tWPH tWC VIH CLK VIL tVCS VCC Notes 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. Amax-A16 are don't care during command sequence unlock cycles. 72 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Figure 19.7 Chip/Sector Erase Operations Erase Command Sequence (last two cycles) tAS AVD tAH tAVDP Amax-A16 SA 555h for chip erase 10h for chip erase Read Status Data VA In Progress VA A/DQ15- A/DQ0 CE# 2AAh 55h SA 30h tDS tDH VA VA Complete OE# tWP WE# tCS tCH tWHWH2 tWPH tWC VIH CLK VIL tVCS VCC Notes 1. SA is the sector address for Sector Erase. 2. Address bits Amax-A16 are don't cares during unlock cycles in the command sequence. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 73 Data Sheet (Advance Information) Figure 19.8 Accelerated Unlock Bypass Programming Timing CE# AVD# WE# Amax-A16 A/DQ15- A/DQ0 CE# ACC VID PA Don't Care A0h PA PD Don't Care tVPS tACC VIL or VIH Notes 1. ACC can be left high for subsequent programming pulses. 2. Use setup and hold times from conventional program operation. Figure 19.9 Data# Polling Timings (During Embedded Algorithm) AVD# tCE CE# tCH OE# tOEH WE# tACC Amax-A16 A/DQ15- A/DQ0 VA VA High Z tCEZ tOE tOEZ High Z VA Status Data VA Status Data Notes 1. All status reads are asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. 74 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Figure 19.10 Toggle Bit Timings (During Embedded Algorithm) AVD# tCE CE# tCH OE# tOEH WE# tACC Amax-A16 A/DQ15- A/DQ0 VA VA High Z tCEZ tOE tOEZ High Z VA Status Data VA Status Data Notes 1. All status reads are asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. Figure 19.11 8-, 16-, and 32-Word Linear Burst Address Wrap Around Address wraps back to beginning of address group. Initial Access CLK Address (hex) A/DQ15- A/DQ0 VIH 39 39 3A 3B 3C 3D 3E 3F 38 D0 D1 D2 D3 D4 D5 D6 D7 AVD# VIL VIH VIL OE# (stays low) (stays low) CE# VIL Note 8-word linear burst mode shown. 16- and 32-word linear burst read modes behave similarly. D0 represents the first word of the linear burst. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 75 Data Sheet (Advance Information) Figure 19.12 Latency with Boundary Crossing Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. C124 CLK Address (hex) AVD# 7C (stays high) C125 7D C126 7E C127 7F C127 7F C128 80 C129 81 C130 82 C131 83 tRACC RDY(1) tRACC RDY(2) latency latency tRACC tRACC Data D124 D125 D126 D127 D128 D129 D130 OE#, CE# (stays low) Notes 1. Cxx indicates the clock that triggers data Dxx on the outputs; for example, C60 triggers D60. 2. At frequencies less than or equal to 66 Mhz, there is no latency. 76 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Figure 19.13 Back-to-Back Read/Write Cycle Timings Last Cycle in Program or Sector Erase Command Sequence Read status (at least two cycles) in same bank and/or array data from other bank Begin another write or program command sequence tWC tRC tRC tWC CE# OE# tOE tOEH WE# tWPH tWP tDS tDH A/DQ15- A/DQ0 PA/SA PD/30h RA RD tGHWL tACC tOEZ tOEH RA RD 555h AAh tSR/W Amax-A16 PA/SA RA RA tAS AVD# tAH Note Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" while checking the status of the program or erase operation in the "busy" bank. The system should read status twice to ensure valid information. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 77 Data Sheet (Advance Information) 20. Erase and Programming Performance Parameter 64 Kword 32 Kword Sector Erase Time 16 Kword 8 Kword VCC VCC VCC VCC Typ (Note 1) 0.8 0.6 0.15 0.12 154 (NS256N) VCC Chip Erase Time 131 (NS256N) ACC 66 (NS128N) 50 (NS064N) Single Word Programming Time Effective Word Programming Time utilizing Program Write Buffer Total 32-Word Buffer Programming Time VCC ACC VCC ACC VCC ACC 40 24 9.4 6 300 192 157.3 (NS256N) VCC Chip Programming Time (Note 4) 101 (NS256N) ACC 51 (NS128N) 26 (NS064N) 202 (NS256N) 102 (NS128N) 52 (NS064N) 78.6 (NS128N) 39.3 (NS064N) 262 (NS256N) 132 (NS128N) 100 (NS064N) 400 240 94 us 60 3000 1920 314.6 (NS256N) 157.3 (NS128N) 78.6 (NS064N) s Excludes system level overhead (Note 6) 77 (NS128N) 58 (NS064N) Max (Note 2) 3.5 3 2 2 308 (NS256N) s 154 (NS128N) 116 (NS064N) Excludes 00h programming prior to erasure (Note 5) Unit Comments Notes 1. Typical program and erase times assume the following conditions: 25C, 1.8 V VCC, 10,000 cycles typical. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 1.70 V, 100,000 cycles. 3. Effective write buffer specification is based upon a 32-word write buffer operation. 4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11.4 on page 54 for further information on command definitions. 21. BGA Ball Capacitance Parameter Symbol CIN COUT CIN2 Notes 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz. Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 4.2 5.4 3.9 Max 5.0 6.5 4.7 Unit pF pF pF 78 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 22. Physical Dimensions (S29NS256N) 22.1 VDC048--48-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 11 x 10 mm Package D A1 CORNER INDEX MARK 10 A D1 A1 CORNER 10 9 8 7 6 5 4 3 2 NF2 1 NF1 NF3 NF4 e E 1.00 NF5 NF6 A B C D SE 7 E1 1.00 NF7 NF8 B 1.00 1.00 b A A1 A2 0.10 C SD 7 6 0.15 M C A B 0.05 M C SEATING PLANE C 0.08 C NOTES: PACKAGE JEDEC VDC 048 N/A 9.95 mm x 10.95 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE ? 0.25 MIN 0.86 0.20 0.66 9.85 10.85 NOM ----0.71 9.95 10.95 4.50 1.50 10 4 48 0.30 0.50 0.25 0.35 MAX 1.00 --0.76 10.05 11.05 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT 8. 9. 10 6 7 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN ? THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 NOT USED. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3241 \ 16-038.9h.aa01 *For reference only. BSC is an ANSI standard for Basic Space Centering S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 79 Data Sheet (Advance Information) 23. Physical Dimensions (S29NS128N) 23.1 VDD044--44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 9.2 x 8 mm Package D A1 CORNER INDEX MARK 10 A D1 A1 CORNER 10 9 8 7 6 5 4 3 2 NF2 1 NF1 e A B C D E 1.00 NF4 NF3 SE 7 E1 1.00 TOP VIEW B SD b 7 6 0.15 M C A B 0.05 M C A A1 A2 0.10 C BOTTOM VIEW SIDE VIEW SEATING PLANE C 0.08 C NOTES: PACKAGE JEDEC VDD 044 N/A 8.00 mm x 9.20 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE 0.25 MIN 0.86 0.20 0.66 7.90 9.10 NOM ----0.71 8.00 9.20 4.50 1.50 10 4 44 0.30 0.50 0.25 0.35 MAX 1.00 --0.76 8.10 9.30 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3239 \ 16-038.9h.aa01 80 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) 23.2 VDE044--44-Ball Very Thin Fine-Pitch Ball Grid Array (FBGA) 7.7 x 6.2mm Package A1 CORNER INDEX MARK 10 D A D1 A1 CORNER 10 9 8 7 6 5 4 3 2 1 NF2 NF1 e A E 1.00 NF4 NF3 B C D SE 7 E1 1.00 TOP VIEW B SD b 7 6 0.05 M C 0.15 M C A B A A1 A2 0.10 C BOTTOM VIEW SIDE VIEW SEATING PLANE C 0.08 C NOTES: PACKAGE JEDEC VDE 044 N/A 7.70 mm x 6.20 mm NOM PACKAGE SYMBOL A A1 A2 D E D1 E1 MD ME N b e SD / SE 0.25 MIN 0.86 0.20 0.66 7.6 6.1 NOM ----0.71 7.7 6.2 4.50 1.50 10 4 44 0.30 0.50 BSC. 0.25 BSC. 0.35 MAX 1.00 --0.76 7.8 6.3 NOTE OVERALL THICKNESS BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE BALL FOOTPRINT BALL FOOTPRINT ROW MATRIX SIZE D DIRECTION ROW MATRIX SIZE E DIRECTION TOTAL BALL COUNT BALL DIAMETER BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 6 7 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN ? THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3308.2 \ 16-038.9L S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 81 Data Sheet (Advance Information) 24. Revision Summary 24.1 Revision A (April 16, 2004) Initial Release. 24.2 Revision A1 (June 28, 2004) General Description Corrected the effective temperature range to -25C to +85C. Connection Diagram Corrected pin B5 on the S29NS256N to A23. Corrected pin B1 on the S29NS256N to VCC. Corrected pin B1 on the S29NS128N to VCC. Corrected pin B1 on the S29NS064N to VCC. Created separate illustrations for S29NS128N and S29NS064N. Ordering Information Corrected the Package Type offerings. Valid Combinations table Included package type description for S29NS064N device. Completely revised format and layout. 8-, 16-, and 32-Word Linear Burst without Wrap Around Corrected information in this section. Lock Register Section and table were substantially revised. Programmable Wait State Corrected information in this section. Handshaking Feature Corrected information in this section. Autoselect Command Sequence Corrected information in this section. Physical Dimensions Corrected the drawing for the S29NS064N device. Write Buffer Command Sequence Corrected the address for the Write Buffer Load sequence. 24.3 Revision A2 (September 9, 2004) Connection Diagrams Updated pin labels. Ordering Information Completely updated the OPN table. Valid Combinations table Updated this table. 82 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Continuous Burst Added information to this section. Lock Register Updated the lock register table. Configuration Register Updated the settings for CR15. Device ID table Updated the indicator bits information. Figure 7 Updated the waveform. Figure 21 Updated the waveform. 24.4 Revision A3 (November 16, 2004) Table "Primary Vendor-Specific Extended Query" Updated the data values for addresses 45h, 53h, and 54h. Global Updated the synchronous and asynchronous access times. Programmable Wait State Updated this section. Write Buffer Programming Command Sequence Added a note to the table. 24.5 Revision A3a (April 5, 2005) Global Updated reference links. Distinctive Characteristics Added note to ACC is represented as VPP in older documentation. General Description Added note regarding ACC and VPP. Block Diagram Added same note regarding ACC and VPP. Added WP# term and arrow to State Control and Command Register block. Block Diagram of Simultaneous Operation Circuit Changed VPP to Vssq. Added WP# term and arrow to State Control and Command Register block. Added ACC term and arrow to State Control and Command Register block. Added note to ACC is represented as VPP in older documentation. Input/Output Description Added VPP term adjacent to ACC term. S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 83 Data Sheet (Advance Information) Tables 2, 3, 4, 5, 6, 7, 8, and 9 Change Wait State titles and columns in these tables. Table 24 Changed Function column and Settings to represent Reserved CR Bits. Table 27 Removed several bold lines between columns. DC Characteristics Reduced Typ and Max values for ICCB. Added note for clock frequency in continuous mode. Erase & Programming Performance Table Corrected Sector Erase Time Typ. Value for 64 Kword from 0.6 to 0.8 in Erase and Programming Performance table Physical Dimensions (S29NS046N) Replaced VDE044 with new package drawing. Device History Updated Device History table 24.6 Revision A4 (April 12, 2005) Global Changes Removed 64Mb density. Removed 54MHz speed option. Changed ACC to VPP. Read Access Times Removed burst access for 54MHz. Defined asynchronous random access and synchronous random access to 80 ns for all speed options. DC Characteristics CMOS Compatible Table. Updated ICC3 and ICC6 values from 40A to 70A. 24.7 Revision A5 (August 15, 2005) Added S29NS064N with new sector and bank architecture. Added VDE044 package type for S29NS064N Erase/Program Operations table Updated description and values for tCS. Device History Updated table with latest revision information. 24.8 Revision A6 (August 24, 2005) AC Characteristics Updated the notes for the VCC Power-up table Erase and Programming Performance Operations 84 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 Data Sheet (Advance Information) Updated max value for 8 Kword Sector Erase Time Updated typical and max values for Chip Programming Time 24.9 Revision A7 (September 16, 2005) Ordering Information Updated the Package Type options Valid Combinations table Updated entire table to show new options 24.10 Revision A8 (September 23, 2005) Dynamic Protection Bit (DYB) Added note: Dynamic protection bits revert back to their default values after programming the device "Lock Register." Lock Register Table Added Note: When the device lock register is programmed (PPB mode lock bit is programmed, password mode lock bit programmed, or the Secured Silicon lock bit is programmed) all DYBs revert to the power-on default state. 24.11 Revision A9 (November 15, 2005) Write Buffer Programming Operation Updated the flowchart 24.12 Revision A10 (March 23, 2006) Asynchronous Read AC Characteristics table Updated the minimum specifications of tAAVDH for both speed bins. Global Change Changed VPP to ACC 24.13 Revision A11 (April 20, 2006) Global Change Changed layout and font Absolute Maximum Ratings Updated Figure 13.1 and 13.2 24.14 Revision A12 (June 13, 2006) Global Change Publication Identification number was incorrectly set to S29NS-N_01 for revision 11 instead of S29NS-N_00. It is corrected in this revision. The document file name was not affected by this error. Added a note to Table 8.1 Device Bus Operations Added a note to Table 11.1 Configuration Register Added a note to section 11.9 Erase Suspend/Erase Resume Commands S29NS-N_00_A13 February 16, 2007 S29NS-N MirrorBitTM Flash Family 85 Data Sheet (Advance Information) Added a note to section 11.10 Program Suspend/Program Resume Commands Added a note to section 11.13 Non-Volatile Sector Protection Command Set Definitions Added a note to section 11.15 Volatile Sector Protection Command Set Modified the "All PPB Erase" row of Table 11.4 Command Definitions (Sheet 2 of 3) Changed VI/O to VCCQ in section 15.1 CMOS Compatible Changed VI/O to VCCQ in Table 16.1 Test Specifications Changed VI/O to VCCQ in Figure 18.1 Input Waveforms and Measurement Levels Added parameters tERS and tPRS in section 19.5 Erase/Program Operations 24.15 Revision A13 (February 16, 2007) Global Change Removed 80MHz ordering option (use 90nm products to support this speed) Updated VDE044 package drawing Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2004-2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. 86 S29NS-N MirrorBitTM Flash Family S29NS-N_00_A13 February 16, 2007 |
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